Semiconductor device

Patent metadata

Field	Value
Publication number	US-2016295690-A1
Application number	US-201615063132-A
Country	US
Kind code	A1
Filing date	Mar 7, 2016
Priority date	Apr 2, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

A semiconductor device includes: a plurality of semiconductor units each including a semiconductor element and a plurality of main terminals that are electrically connected to the semiconductor element, the plurality of semiconductor units being arranged in a same plane with a same orientation in a plan view; and a connecting unit that electrically connects in parallel the semiconductor units arranged in substantially the same plane, the connecting unit having a plurality of external terminals that are respectively connected to the main terminals of each of the semiconductor units, wherein a geometrical arrangement of the main terminals, in a plan view, of each of the semiconductor units relative to an overall plan-view shape of the semiconductor unit and a geometrical arrangement of the external terminals, in a plan view, of the connecting unit relative to an overall plan-view shape of the connecting unit have a substantial geometrical similarity with each other.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a plurality of semiconductor units each including a semiconductor element and a plurality of main terminals that are electrically connected to the semiconductor element, the plurality of semiconductor units being arranged in a same plane with a same orientation in a plan view; and a connecting unit that electrically connects in parallel the semiconductor units arranged in substantially the same plane, the connecting unit having a plurality of external terminals that are respectively connected to the main terminals of each of the semiconductor units, wherein a geometrical arrangement of the main terminals, in a plan view, of each of the semiconductor units relative to an overall plan-view shape of the semiconductor unit and a geometrical arrangement of the external terminals, in a plan view, of the connecting unit relative to an overall plan-view shape of the connecting unit have a substantial geometrical similarity with each other.

2 . The semiconductor device according to claim 1 ,
wherein each semiconductor unit includes four main terminals, wherein the connecting unit includes four external terminals, wherein the four main terminals of each semiconductor unit are arranged in two columns, and wherein the four external terminals of the connecting unit are arranged in two columns.

3 . The semiconductor device according to claim 1 ,
wherein each semiconductor unit includes three main terminals, wherein the connecting unit includes three external terminals, wherein the three main terminals of each semiconductor unit are arranged in one column, and wherein the three external terminals of the connecting unit are arranged in one column.

4 . The semiconductor device according to claim 1 ,
wherein the connecting unit further includes a plurality of circuit layers, and wherein the main terminals are electrically connected to the corresponding external terminals via the circuit layers.

5 . The semiconductor device according to claim 1 ,
wherein the semiconductor units are arranged in one column, and wherein each of the external terminals is arranged so as to be at a same distance to the corresponding main terminals on the semiconductor units that are arranged at respective ends of said one column.

6 . The semiconductor device according to claim 1 ,
wherein the semiconductor units are arranged both horizontally and vertically with at least two semiconductor units in each direction, thereby forming a rectangular arrangement in a plan view, and wherein each of the external terminals is arranged so as to be at a same distance to the corresponding main terminals on the semiconductor units that are located at respective four corners of the rectangular arrangement.

7 . The semiconductor device according to claim 1 , wherein each of the semiconductor units constitutes a three-level inverter circuit.

8 . The semiconductor device according to claim 1 , wherein each of the semiconductor units constitutes a two-level inverter circuit.

9 . The semiconductor device according to claim 1 , wherein each of the semiconductor units constitutes a three-level inverter circuit in which four external terminals are arranged in two columns.

Assignees

• Fuji Electric Co Ltd

Inventors

• Takano Sho

Classifications

• H05K1/0296 Primary

  Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295 (H05K1/11 takes precedence; lay-out adapted to mounted component configuration H05K1/18) · CPC title

• H02M7/003 Primary

  Constructional details, e.g. physical layout, assembly, wiring or busbar connections · CPC title

• H05K1/0298

  Multilayer circuits · CPC title

• H05K1/181

  associated with surface mounted components · CPC title