Imaging systems with real-time digital testing capabilities

Patent metadata

Field	Value
Publication number	US-2016295205-A1
Application number	US-201514675877-A
Country	US
Kind code	A1
Filing date	Apr 1, 2015
Priority date	Apr 1, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

An imaging system with real-time digital testing capabilities verifies the functionality of image processing circuitry used to process pixel data signals read out from a pixel array during imaging operations. Image processing circuitry may process a data frame read from an imaging array that includes multiple regions of imaging and non-imaging data. Digital test patterns may be generated to test the functionality of specific image processing blocks. Test patterns may correspond to or represent imaging data or non-imaging data from regions of the output readout frame. A checksum generator generates a test pattern checksum for output of a subset of the image processing blocks that were provided with a given test pattern. The test pattern checksum may be compared to a predetermined checksum of the output of properly functioning image processing blocks provided with test patterns equivalent to the given test pattern.

First claim

What is claimed is:

1 . Image processing circuitry that produces an output data frame during a frame time interval, comprising:
control circuitry coupled to an image sensor, wherein the image sensor comprises a plurality of pixels arranged in rows and columns, wherein the control circuitry is configured to output a first set of data during a first portion of the frame time interval and a second set of data during a second portion of the frame time interval that is subsequent to the first portion; a plurality of image processing blocks that are configured to process the first and second sets of row data output by the control circuitry; and a test pattern generator that is configured to output test patterns to the plurality of image processing blocks during the second portion of the frame time interval.

2 . The image processing circuitry defined in claim 1 , wherein the first set of data comprises data of a first type, wherein the second set of data comprises data of a second type, and wherein the plurality of image processing blocks comprises:
a first subset of image processing blocks that is configured to process data of the first type; and a second subset of image processing blocks that is configured to process data of the second type.

3 . The image processing circuitry defined in claim 2 , wherein the test pattern generator is configured to output test patterns corresponding to the second type of data during at least part of the second portion of the frame time interval, and wherein the second subset of image processing blocks are configured to process the test patterns based on the second type of data to produce a processed test value.

4 . The image processing circuitry defined in claim 3 , further comprising:
a checksum generator, wherein the checksum generator is configured to generate a checksum value based on the processed test value, to compare the generated checksum value to a predetermined checksum value, and to assert an error signal when the generated checksum value is different from the predetermined checksum value.

5 . The image processing circuitry defined in claim 4 , wherein the test pattern generator is configured to output test patterns corresponding to the first type of data during at least a part of the first portion of the frame time interval, wherein the first subset of image processing blocks are configured to process the test patterns based on the first type of data to produce an additional processed test value, and wherein the checksum is further configured to generate a checksum based on the processed test value and the additional processed test value.

6 . The image processing circuitry defined in claim 3 , wherein the first type of data comprises digital test data, wherein the second type of data comprises pixel data, and wherein the test pattern generator is further configured to output test patterns corresponding to digital test data during the entire first portion of the frame time interval.

7 . The image processing circuitry defined in claim 3 , wherein the test pattern generator is configured to output test patterns corresponding to the second type of data during the entire second portion of the frame time interval.

8 . The image processing circuitry defined in claim 1 , wherein the digital test pattern generator comprises:
a plurality of pattern generator blocks, comprising:
a standard pattern generator;
a definable pattern generator;
a noise generator; and
a cursor generator; and
a region enable register that selectively includes respective outputs of the plurality of pattern generator blocks in the generated digital test pattern.

9 . The image processing circuitry defined in claim 8 , wherein the region enable register is configured to include outputs of a first subset of the plurality of pattern generator blocks into the generated digital test pattern so that the generated digital test pattern corresponds to a first data type associated with a first region data generated by the image sensor pixel array, and wherein the region enable register is configured to include outputs of a second subset of the plurality of pattern generator blocks into the generated digital test pattern so that the generated digital test pattern corresponds to a second data type associated with a second region data generated by the image sensor pixel array.

10 . The image processing circuitry defined in claim 8 , wherein the digital test pattern generator is configured to generate the digital test pattern by overlaying the outputs of the plurality of pattern generator blocks that are selectively included in the generated digital test pattern by the region enable register.

11 . A method of operating an imaging system during a frame time interval that is the inverse of an operating frame rate of the imaging system, wherein the imaging system comprises an array of image sensor pixels, test pattern generator circuitry, image processing circuits, and pixel readout circuitry, the method comprising:
with the test pattern generator circuitry, generating a digital test pattern based on a frame of data generated by the array; with a first subset of the image processing circuits, processing the digital test pattern to produce a test output value; with the pixel readout circuitry, reading out image signals from the pixel array to produce image pixel data; and with a second subset of the image processing circuits, processing the image pixel data to produce processed image pixel data.

12 . The method defined in claim 11 , wherein the frame of data comprises at least first and second regions, wherein the first and second regions are associated with first and second data types respectively, wherein the image data is of the first data type, and wherein generating the digital test pattern comprises:
generating a digital test pattern corresponding to a given data type, wherein the first subset is the same as the second subset when the given data type is the first data type, and wherein the first subset is different than the second subset when the given data type is the second data type.

13 . The method defined in claim 11 , further comprising:
with checksum circuitry, generating a test result checksum value based on the test output value.

14 . The method defined in claim 13 , further comprising:
with the checksum circuitry, comparing the test result checksum value to an expected test checksum value; and with the checksum circuitry, asserting an error signal when the test result checksum value is different from the expected test checksum value.

15 . The method defined in claim 11 , wherein reading out pixel signals from the pixel array comprises reading out at least one signal selected from the group of signals consisting of: row noise correction pixel signals and optically dark pixel signals.

16 . The method defined in claim 11 , wherein the frame of data comprises at least first and second regions, wherein the first and second regions are associated with first and second data types respectively, and wherein the digital test pattern corresponds to the first data type, the method further comprising:
with the test pattern generator circuitry, generating an additional digital test pattern, wherein the additional digital test pattern is based on the second data type; and with a third subset of the image processing circuits, processing the additional digital test pattern to produce an additional test output value.

17 . The method defined in claim 11 , further comprising:
with data checking circuitry, performing Automotive Safety Inte

Assignees

• Semiconductor Components Ind Llc

Inventors

• Lim Yan Ping
• Engelbrecht Dennis
• Davis Raymond Allen
• Hernandez Agustin

Classifications

• H04N17/002 Primary

  for television cameras · CPC title

• H04N25/70

  SSIS architectures; Circuits associated therewith · CPC title

• H04N23/683

  performed by a processor, e.g. controlling the readout of an image memory · CPC title