Solid-state image pickup device and method for driving the same in solid-state imaging pickup device and method for driving the same in a number of modes

Patent metadata

Field	Value
Publication number	US-2016295145-A1
Application number	US-201615180300-A
Country	US
Kind code	A1
Filing date	Jun 13, 2016
Priority date	Feb 23, 2004
Publication date	Oct 6, 2016
Grant date	—

Abstract

A system and method for driving a solid-state image pickup device including a pixel array unit including unit pixels. Each unit pixel includes a photoelectric converter, column signal lines and a number of analog-digital converting units. The unit pixels are selectively controlled in units of rows. Analog signals output from the unit pixels in a row selected by the selective control though the column signal lines are converted to digital signals via the analog-digital converting units. The digital signals are added among a number of unit pixels via the analog-digital converting units. The added digital signals from the analog-digital converting units are read. Each unit pixel in the pixel array unit is selectively controlled in units of arbitrary rows, the_analog-distal converting units being operable to performing the converting in a (a) normal-frame-rate mode and a (b) high-frame-rate mode in response to control signals.

First claim

1 - 5 . (canceled)

6 . An imaging device comprising:
a pixel array unit including a plurality of pixels which are two-dimensionally arranged in columns and rows; a plurality of lines including a first line coupled to a pixel of the plurality of pixels and a second line disposed adjacent to the first line; a plurality of A/D converters including a plurality of comparators and a plurality of memories; and a switch circuit; wherein,
a comparator of the plurality of comparators is coupled to the first line and the second line through the switch circuit,
the comparator is configured to output a first signal based on an output of the first line and a second signal based on an output of the second line, and
a memory of the plurality of memories is configured to receive a third signal based on the first signal and a fourth signal based on the second signal.

7 . The imaging device according to claim 6 , further comprising a reference signal generation circuit that supplies a reference signal to the comparator.

8 . The imaging device according to claim 6 , wherein the second line is coupled to at least one pixel of the plurality of pixels.

9 . The imaging device according to claim 6 , wherein the plurality of A/D converters includes a plurality of counters.

10 . The imaging device according to claim 9 , wherein the memory is coupled to a counter of the plurality of counters.

11 . The imaging device according to claim 10 , wherein the memory is configured to receive the third signal based on the first signal and the fourth signal based on the second signal through the counter of the plurality of counters.

12 . The imaging device according to claim 11 , wherein each pixel of the plurality of the pixels includes a photoelectric conversion element, a reset transistor, a transfer transistor, an amplifier transistor, and a select transistor.

13 . An imaging device comprising:
a pixel array unit including a plurality of pixels which are two-dimensionally arranged in columns and rows, the plurality of pixels including a first pixel and a second pixel; a plurality of lines including a first line coupled to the first pixel, a second line disposed adjacent to the first line, a third line coupled to the second pixel, and a fourth line disposed adjacent to the third line; a first switch circuit; a second switch circuit; and a plurality of A/D converters including: a plurality of comparators including a first comparator that outputs a first signal based on an output of the first line and a second signal based on an output of the second line and a second comparator that outputs a third signal based on an output of the third line and a fourth signal based on an output of the fourth line, and a plurality of memories including a first memory and a second memory, wherein,
the first comparator is coupled to the first line and the second line through the first switch circuit, the second comparator is coupled to the third line and the fourth line through the second switch circuit, the first memory is configured to receive a fifth signal based on the first signal and a sixth signal based on the second signal, and the second memory circuit is configured to receive a seventh signal based on the third signal and an eighth signal based on the fourth signal.

14 . The imaging device according to claim 13 , further comprising a reference signal generation circuit that supplies a reference signal to the first comparator and the second comparator.

15 . The imaging device according to claim 13 , wherein the second line is coupled to at least one pixel of the plurality of pixels.

16 . The imaging device according to claim 13 , wherein the fourth line is coupled to at least one pixel of the plurality of pixels.

17 . The imaging device according to claim 13 , wherein the plurality of A/D converters includes a plurality of counters.

18 . The imaging device according to claim 17 , wherein the plurality of counters includes a first counter coupled to the first memory and a second counter coupled to the second memory.

19 . The imaging device according to claim 18 , wherein the first memory is configured to receive the fifth signal based on the first signal and a sixth signal based on the second signal through the first counter, and the second memory circuit is configured to receive the seventh signal based on the third signal and the eighth signal based on the fourth signal through the second counter.

20 . The imaging device according to claim 13 , wherein each pixel of the plurality of the pixels includes a photoelectric conversion element, a reset transistor, a transfer transistor, an amplifier transistor, and a select transistor.

21 . An imaging device comprising:
a pixel array unit including a plurality of pixels which are two-dimensionally arranged in columns and rows, the plurality of pixels including a first pixel; a plurality of lines including a first line coupled to the first pixel, a second line disposed adjacent to the first line; a switch circuit; a first comparator coupled to the first line and the second line via the switch circuit, wherein the first comparator outputs a first signal based on an output of the first line and a second signal based on an output of the second line; a second comparator coupled to first line and the second line via the switch circuit, wherein the second comparator outputs a third signal based on the output of the first line and a fourth signal based on the output of the second line; a first memory circuit that receives a fifth signal based on the first signal, and a sixth signal based on the second signal; and a second memory circuit that receives a seventh signal based on the third signal and an eighth signal based on the fourth signal.

22 . The imaging device according to claim 21 , further comprising a reference signal generation circuit that supplies a reference signal to the first comparator and the second comparator.

23 . The imaging device according to claim 21 , wherein the second line is coupled to at least one pixel of the plurality of pixels.

24 . The imaging device according to claim 21 , further comprising a plurality of counters

25 . The imaging device according to claim 24 , wherein the plurality of counters includes a first counter coupled to the first memory and a second counter coupled to the second memory.

26 . The imaging device according to claim 25 , the first memory is configured to receive the fifth signal based on the first signal and the sixth signal based on the second signal through the first counter, and the second memory circuit is configured to receive the seventh signal based on the third signal and the eighth signal based on the fourth signal through the second counter.

27 . The imaging device according to claim 21 , wherein each pixel of the plurality of the pixels includes a photoelectric conversion element, a reset transistor, a transfer transistor, an amplifier transistor, and a select transistor.

Assignees

• Sony Corp

Inventors

• Nitta Yoshikazu
• Fukushima Noriyuki
• Muramatsu Yoshinori
• Yasui Yukihiko

Classifications

• H03M1/56

  Input signal compared with linear ramp · CPC title

• H03M1/1023 Primary

  Offset correction (H03M1/1019 takes precedence; removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H04N23/54

  Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils · CPC title

• H04N25/46

  by combining or binning pixels · CPC title

• H04N25/767

  Horizontal readout lines, multiplexers or registers · CPC title