Electronic drive circuit and method

Patent metadata

Field	Value
Publication number	US-2016294384-A1
Application number	US-201615060234-A
Country	US
Kind code	A1
Filing date	Mar 3, 2016
Priority date	Mar 31, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

Disclosed is an electronic drive circuit and a drive method. The drive circuit includes an output; a first output transistor comprising a control node and a load path, wherein the load path is coupled between the output and a first supply node; a voltage regulator configured to control a voltage across the load path of the first output transistor; and a first driver configured to drive the first output transistor based on a first control signal.

First claim

1 . A drive circuit, comprising:
an output; a first output transistor comprising a control node and a load path, wherein the load path is coupled between the output and a first supply node; a voltage regulator configured to control a voltage across the load path of the first output transistor; and a first driver configured to drive the first output transistor based on a first control signal.

2 . The drive circuit of claim 1 , wherein the voltage regulator comprises:
a regulator transistor comprising a control node and load path, wherein the load path is connected in series with the load path of the first output transistor, and wherein a series circuit with the load path of the regulator transistor and the load path of the first output transistor is connected between the output and the first supply node; and a biasing voltage source coupled between the control node of the regulator transistor and a first load path node of the first output transistor.

3 . The drive circuit of claim 2 , wherein the load path node of the first output transistor is connected to the output.

4 . The drive circuit of claim 1 , wherein the first driver comprises:
a first resistor connected between the control node and a first load path node of the first output transistor; and a first current source configured to drive a first current through the first resistor based on the first control signal.

5 . The drive circuit of claim 4 , wherein the first driver further comprises:
a second resistor and a second current source configured to drive a current through the second resistor; and a first amplifier connected between a circuit node common to the second resistor and the second current source and the control node of the first output transistor.

6 . The drive circuit of claim 5 , wherein the first amplifier comprises a push-pull stage configured to operate in one of a current source mode and a current sink mode based on a current provided by the second current source.

7 . The drive circuit of claim 6 ,
wherein the first current source, controlled by a control circuit, is configured to generate different current levels of the first current through the first resistor, and wherein the second current source, controlled by the control circuit, is configured to operate the amplifier in the current source mode when the current level of the first current through the first resistor increases, and in the current sink mode when the current level of the first current through the first resistor decreases.

8 . The drive circuit of claim 2 , wherein the first output transistor and the regulator transistor are transistors of the same conductivity type.

9 . The drive circuit of claim 8 , wherein each of the first output transistor and the regulator transistor is a MOSFET.

10 . The drive circuit of claim 1 , further comprising:
an electronic switch connected between the output and a second supply node; and a second driver configured to drive the electronic switch based on a second control signal.

11 . The drive circuit of claim 10 , wherein the electronic switch comprises a second output transistor comprising a control node and a load path, wherein the load path is connected between the output and the second supply node.

12 . The drive transistor of claim 11 , wherein the first output transistor and the second output transistor are transistors of the same conductivity type.

13 . The drive circuit of claim 11 , wherein the second driver comprises:
a third resistor connected between the control node and a first load path node of the second output transistor; and a second current source configured to drive a current through the second resistor based on the second control signal.

14 . The drive circuit of claim 13 , wherein the second driver further comprises:
a third resistor and a third current source configured to drive a current through the third resistor; and a second amplifier connected between a circuit node common to the second resistor and the second current source and the control node of the second output transistor.

15 . The drive circuit of claim 13 further comprising:
a control circuit configured to generate the first control signal and the second control signal based on an input signal of the drive circuit.

16 . The drive circuit of claim 1 , further comprising:
a clamping circuit configured to deactivate the voltage regulator based on a voltage between the output and the second supply node.

17 . The drive circuit of claim 16 , wherein the clamping circuit is further configured to clamp a voltage between the output and the second supply node.

18 . The drive circuit of claim 16 , wherein the clamping circuit is further configured to clamp a voltage across the load path of the first output transistor.

19 . A method, comprising:
driving a first output transistor coupled to an output of a drive circuit by a first driver based on a first control signal, and controlling a voltage across the load path of the first output transistor by a voltage regulator.

20 . The method of claim 19 , wherein the voltage regulator comprises:
a regulator transistor comprising a control node and load path, wherein the load path is connected in series with the load path of the first output transistor, and wherein a series circuit with the load path of regulator transistor and the load path of the first output transistor is connected between the output and the first supply node; and a biasing voltage source coupled between the control node of the regulator transistor and a first load path node of the first output transistor.

21 . The method of claim 19 , wherein driving the first output transistor comprises:
driving a first current through a first resistor based on the first control signal by a first current source, wherein the first resistor is connected between the control node and a first load path node of the first output transistor.

22 . The method of claim 21 wherein driving the first output transistor further comprises:
driving a second current through a second resistor by a second current source; and
operating a first amplifier connected between a circuit node common to the second resistor and the second current source and the control node of the first output transistor in one of a current source mode and a current sink mode based on a current provided by the second current source.

23 . The method of claim 21 , the method further comprising: generating different current levels of the first current by the first current source, controlled by a control circuit, and
by the second current source controlled by the control circuit, operating the amplifier in the current source mode when the current level of the first current through the first resistor increases, and in the current sink mode when the current level of the first current through the first resistor decreases.

24 . The method of claim 19 , the method further comprising:
deactivating the voltage regulator based on a voltage between the output and a supply node.

25 . The method of claim 24 , the method further comprising:
clamping a voltage between the output and the supply node.

26 . The method of claim 19 , the method further comprising:
driving an MOS transistor by the first output transistor.

Assignees

• Infineon Technologies Ag

Inventors

• Schindler Alexis
• Wicht Bernhard
• Zannoth Markus

Classifications

• H03K5/08 Primary

  by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding (H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30) · CPC title

• H03K17/687 Primary

  the devices being field-effect transistors · CPC title

• H03K19/018557 Primary

  Coupling arrangements; Impedance matching circuits · CPC title

• H03K17/04123

  in field-effect transistor switches · CPC title

• H03K17/162

  without feedback from the output circuit to the control circuit · CPC title