Bit-Capture Latch with Transparency Option

Patent metadata

Field	Value
Publication number	US-2016294371-A1
Application number	US-201514677366-A
Country	US
Kind code	A1
Filing date	Apr 2, 2015
Priority date	Apr 2, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

A novel and simple way is presented to implement a zero-capture latch circuit comprising a pair of OR AND Invert gates connected to achieve a zero-capture latch with transparency option, the output of said zero-capture latch configured to latch the input and store a zero, in functional mode, and a buffered version of the input, in test mode. A one-capture latch circuit comprising a pair of AND OR Invert gates connected to achieve a one-capture latch with transparency option, the output of said one-capture latch configured to latch the input and store a one, in functional mode, and a buffered version of the input, in test mode, is also presented. The need for a test multiplexer is eliminated, reducing the area, complexity and propagation delay of the latch circuit. The propagation delay remains constant, regardless of the mode of operation is functional or test.

First claim

What is claimed is:

1 . A zero-capture latch circuit comprising:
a) a pair of OR AND Invert (OAI) gates connected to achieve a zero-capture latch with transparency option; b) the output of said zero capture latch circuit configured to latch the input and store a zero, in functional mode; and c) the output of said zero-capture latch circuit configured as a buffered version of the input, in test mode.

2 . The zero-capture latch circuit of claim 1 , wherein
a) each of said OAI gates comprises an OR gate and an NAND gate; b) an output of said second OAI gate is connected to an OR gate input of said first OAI gate; c) an output of said first OAI gate is connected to a NAND gate input of said second OAI gate; d) a second input is common to an OR gate in both OAI gates; e) an additional input is connected to an OR gate input of said second OAI gate; f) an additional input is connected to a NAND gate input of said first OAI gate; g) said OR AND Invert gate comprises a plurality of transistors.

3 . The zero-capture latch circuit of claim 1 , wherein said OR AND Invert gates are CMOS transistors.

4 . The zero-capture latch circuit of claim 1 , wherein said additional input connected to said NAND gate input of said first OAI gate is capable of providing a signal to be latched by said zero-capture latch circuit.

5 . The zero-capture latch circuit of claim 1 , wherein said zero-capture latch circuit is capable of the following:
a) if said second input common to said OR gate in said OAI gates and said additional input connected to said OR gate input of said second OAI gate are both zero, said output of said second OAI gate captures a one; b) if said additional input connected to said OR gate input of said second OAI gate is one, said output of said second OAI gate captures a zero; c) if said second input common to said OR gates in said OAI gates is one, said output of said second OAI gate is a buffered version of said additional input connected to said NAND gate input of said first OAI gate.

6 . A one-capture latch circuit comprising:
a) a pair of AND OR Invert (AOI) gates connected to achieve a one-capture latch with transparency option; b) the output of said one-capture latch circuit configured to latch the input and store a one, in functional mode; and c) the output of said one-capture latch circuit configured as a buffered version of the input, in test mode.

7 . The one-capture latch circuit of claim 6 , wherein
a) each of said AOI gates comprises a NOR gate and an AND gate; b) an output of said second AOI gate is connected to an AND gate input of said first AOI gate; c) an output of said first AOI gate is connected to a NOR gate input of said second AOI gate; d) a second input is common to an AND gate in both AOI gates; e) an additional input is connected to an AND gate input of said second AOI gate; f) an additional input is connected to a NOR gate input of said first AOI gate; g) said AND OR Invert gate comprises a plurality of transistors.

8 . The one-capture latch circuit of claim 6 , wherein said AND OR Invert gates are CMOS transistors.

9 . The one-capture latch circuit of claim 6 , wherein said additional input connected to said NOR gate input of said first AOI gate is capable of providing a signal to be latched by said one-capture latch circuit.

10 . The one-capture latch circuit of claim 6 , wherein said one-capture latch circuit is capable of the following:
a) if said second input common to said AND gate in said AOI gates and said additional input connected to said AND gate input of said second AOI gate are both one, said output of said second AOI gate captures a zero; b) if said additional input connected to said AND gate input of said second AOI gate is zero, said output of said second AOI gate captures a one; c) if said second input common to said AND gates in said AOI gates is zero, said output of said second AOI gate is a buffered version of said additional input connected to said NOR gate input of said first AOI gate.

11 . A method for forming a zero-capture latch circuit having a constant propagation delay in both functional and test modes, comprising the steps of:
a) providing a pair of OR AND Invert (OAI) gates connected to achieve a zero-capture latch with transparency option; b) wherein the output of said zero-capture latch circuit latches the input and stores a zero, in functional mode; c) wherein the output of said zero-capture latch circuit buffers a version of the input, in test mode; d) capturing a one at said output of said second OAI gate if said second input common to said OR gate in said OAI gates and said additional input connected to said OR gate input of said second OAI gate are both zero; e) capturing a zero at said output of said second OAI gate if said additional input connected to said OR gate input of said second OAI gate is one; f) buffering a version of said additional input connected to said NAND gate input of said first OAI gate, at said output of said second OAI gate, if said second input common to said OR gates in said OAI gates is one.)

12 . The method of claim 11 , wherein said OR AND Invert (OAI) gates connected to achieve a zero-capture latch with transparency option provide continuous operation in both functional and test mode, reducing size and complexity of said OAI gates, resulting in a significant advance in the state of the art.

13 . A method for forming a one-capture latch circuit having a constant propagation delay in both functional and test modes, comprising the steps of:
a) providing a pair of AND OR Invert (AOI) gates connected to achieve a one-capture latch with transparency option; b) wherein the output of said one-capture latch circuit latches the input and stores a one, in functional mode; c) wherein the output of said one-capture latch circuit buffers a version of the input, in test mode; d) capturing a zero at said output of said second AOI gate if said second input common to said AND gate in said AOI gates and said additional input connected to said AND gate input of said second AOI gate are both one; e) capturing a one at said output of said second AOI gate if said additional input connected to said AND gate input of said second AOI gate is zero; f) buffering a version of said additional input connected to said NOR gate input of said first AOI gate, at said output of said second AOI gate, if said second input common to said AND gates in said AOI gates is zero.

14 . The method of claim 13 , wherein said AND OR Invert (AOI) gates connected to achieve a one-capture latch with transparency option provide continuous operation in both functional and test mode, reducing size and complexity of said AOI gates, resulting in a significant advance in the state of the art.

15 . A threshold comparator circuit, comprising
a) a comparator which compares a fixed reference to a varying input and trips when said input crosses said fixed reference; b) a latch which captures a zero at its output until it is set to one. c) a latch which captures a one at its output until it is reset to zero.

16 . The threshold comparator circuit of claim 15 , wherein
a) said comparator has a fixed reference input and a varying input; b) an output of said comparator is connected to a gate input of a transistor; c) said transistor has a drain common to a current source and a driver; d) an output of said driver is connected to a latch input; e) an input of said latch is for data; f) an additional input of said latch is for function or test mode selection.

Assignees

• Dialog Semiconductor Uk Ltd

Inventors

• Tomatsopoulos Billy

Classifications

• H03K3/356104

  using complementary field-effect transistors (H03K3/35625 takes precedence) · CPC title

• H03K3/037 Primary

  Bistable circuits · CPC title