Systems and methods for controlling inverters

Patent metadata

Field	Value
Publication number	US-2016294303-A1
Application number	US-201514678334-A
Country	US
Kind code	A1
Filing date	Apr 3, 2015
Priority date	Apr 3, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

A method of controlling an inverter includes receiving a target waveform for output voltage of an inverter phase, calculating a phase bias for an inverter phase using the target waveform, biasing the target waveform using the phase bias, and generating a switching device command signal by comparing the biased target waveform to a carrier waveform. The switching device command signal has a switching patter that reduces midpoint current in an inverter input lead and common mode voltage in an inverter output lead.

First claim

What is claimed is:

1 . A method of controlling an inverter, comprising:
receiving a target waveform for output voltage of an inverter phase; calculating a phase bias for an inverter phase using the target waveform; biasing the target waveform using the phase bias; and generating a switching device command signal by comparing the biased target waveform to a carrier waveform, wherein the switching device command signal reduces midpoint current in an inverter input lead and common mode voltage in an inverter output lead.

2 . A method as recited in claim 1 , wherein the target waveform includes an A-phase target waveform, wherein the method further includes receiving B-phase and C-phase target waveforms.

3 . A method as recited in claim 1 , wherein the phase bias includes an A-phase bias, wherein the method further includes calculating a B-phase bias and a C-phase bias.

4 . A method as recited in claim 1 , wherein biasing the target waveform further comprises generating first and second reference signals using the target waveform.

5 . A method as recited in claim 4 , further including:
adding the phase bias to the first reference signal; and subtracting the phase from the second reference signal.

6 . A method as recited in claim 4 , wherein the switching command signal is an upper switch command signal, and further including:
generating the upper switch command signal by comparing the first switching command signal to a first carrier wave; and generating an intermediate lower switch command signal using an inverse of the output of the first switching command signal and first carrier wave comparison.

7 . A method as recited in claim 6 , further including:
generating an intermediate upper switch command signal by comparing the second switching command signal to a second carrier wave; and generating a lower switch command signal using an inverse of the output of the second switching command signal and second carrier wave comparison.

8 . A method as recited in claim 1 , wherein calculating the phase bias further comprises comparing an uncompensated midpoint duty cycle to a target midpoint duty cycle for a phase of the inverter.

9 . A method as recited in claim 8 , wherein the uncompensated midpoint duty cycle for a phase of the inverter is calculated by consolidating output of low and high saturation blocks using the target waveform.

10 . A method as recited in claim 8 , wherein the target midpoint duty cycle is calculated by inverting and biasing a maximum of the absolute value of the plurality of target waveforms.

11 . A control system for an inverter, comprising:
a processor; and a memory communicative with the processor, wherein the processor has instructions recorded thereon that, when read by the processor, cause the processor to:
receive a target waveform representative of output voltage of an inverter phase;
calculate a phase bias for an inverter phase using the target waveform;
bias the target waveform using the phase bias; and
generate a switching device command signal by comparing the biased target waveform to a carrier waveform, wherein the switching device command signal reduces midpoint current in an inverter input lead and common mode voltage in an inverter output lead.

12 . A control system as recited in claim 11 , wherein the instructions further cause the processor to bias the target waveform by generating first and second reference signals using the target waveform.

13 . A control system as recited in claim 12 , wherein the instructions further cause the processor to add the phase bias to the first reference signal and subtract the phase bias from the second reference signal.

Assignees

• Hamilton Sundstrand Corp

Inventors

• White Adam M

Classifications

• H02M7/537 Primary

  using semiconductor devices only, e.g. single switched pulse inverters · CPC title

• H02M7/4833 Primary

  Capacitor voltage balancing · CPC title

• H02M1/0025

  Arrangements for modifying reference values, feedback values or error values in the control loop of a converter · CPC title

• H02M1/123

  Suppression of common mode voltage or current · CPC title

• H02M7/487

  Neutral point clamped inverters · CPC title