Systems and Methods for Producing Carbon Solids
US-2024417566-A1 · Dec 19, 2024 · US
Transister devices with tapered suspended vertical arrays of carbon nanotubes
US2016293871A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016293871-A1 |
| Application number | US-201514674339-A |
| Country | US |
| Kind code | A1 |
| Filing date | Mar 31, 2015 |
| Priority date | Mar 31, 2015 |
| Publication date | Oct 6, 2016 |
| Grant date | — |
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- Title
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Abstract
Official abstract text for this publication.
A transistor device includes an array of fin structures arranged on a substrate, each of the fin structures being vertically alternating stacks of a first isoelectric point material having a first isoelectric point and a second isoelectric point material having a second isoelectric point that is different than the first isoelectric point; one or more carbon nanotubes (CNTs) suspended between the fin structures and contacting a side surface of the second isoelectric point material in the fin structures; a gate wrapped around the array of CNTs; and source and drain contacts arranged over the fin structures; wherein each of the fin structures have a trapezoid shape or parallel sides that are oriented about 90° with respect to the substrate.
First claim
Opening claim text (preview).
1 .- 20 . (canceled) 21 . A transistor device, comprising: a source and a drain arranged on a substrate; an array of carbon nanotubes (CNTs) suspended between the source and the drain, the array of CNTs comprising vertically stacked CNTs having first ends anchored in the source and second ends anchored in the drain, and the array of CNTs being stacked in a tapered orientation with respect to an axis perpendicular to the substrate.
Assignees
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Classifications
Carbon nanotubes, CNTs · CPC title
Field effect transistors, FETS, with nanowire- or nanotube-channel region · CPC title
Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title
- B82Y30/00Primary
Nanotechnology for materials or surface science, e.g. nanocomposites · CPC title
Manufacture or treatment of nanostructures · CPC title
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Frequently asked questions
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- What does patent US2016293871A1 cover?
- A transistor device includes an array of fin structures arranged on a substrate, each of the fin structures being vertically alternating stacks of a first isoelectric point material having a first isoelectric point and a second isoelectric point material having a second isoelectric point that is different than the first isoelectric point; one or more carbon nanotubes (CNTs) suspended between th…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification B82Y30/00. Mapped technology areas include Operations & Transport.
- When was this patent published?
- Publication date Thu Oct 06 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).