Self-aligned vertical cnt array transistor

Patent metadata

Field	Value
Publication number	US-2016293668-A1
Application number	US-201514744132-A
Country	US
Kind code	A1
Filing date	Jun 19, 2015
Priority date	Mar 31, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

A transistor device includes an array of fin structures arranged on a substrate, each of the fin structures being vertically alternating stacks of a first isoelectric point material having a first isoelectric point and a second isoelectric point material having a second isoelectric point that is different than the first isoelectric point; one or more carbon nanotubes (CNTs) suspended between the fin structures and contacting a side surface of the second isoelectric point material in the fin structures; a gate wrapped around the array of CNTs; and source and drain contacts arranged over the fin structures; wherein each of the fin structures have a trapezoid shape or parallel sides that are oriented about 90° with respect to the substrate.

First claim

1 . A method of making a transistor device, the method comprising:
forming an array of fin structures, the array of fin structures being arranged on a substrate and each having a pair of layers, the pair of layers comprising a first isoelectric point material having a first isoelectric point and a second isoelectric point material having a second isoelectric point that is different than the first isoelectric point; wrapping a gate around carbon nanotubes (CNTs) between the fin structures to suspend the CNTs in the gate, the CNTs contacting a side surface of the second isoelectric point material in the fin structures; and forming source and drain contacts over the fin structures; wherein the CNTs are arranged in a substantially vertical array or a non-vertical tapered array within the gate, and the gate comprises a metal gate material separated from the source and drain contacts by a gate spacer and a gate dielectric material.

2 . The method of claim 1 , wherein a gate dielectric material surrounds the CNTs and is hafnium oxide, aluminum oxide, or a combination thereof.

3 . The method of claim 1 , wherein the CNTs are anchored in the source and drain contacts.

4 . (canceled)

5 . The method of claim 1 , wherein each of the fin structures have a width that is less than a length of the fin structure.

6 . The method of claim 1 , wherein the CNTs contact the second isoelectric point material by an electrostatic interaction.

7 . The method of claim 1 , further comprising a positively charged surface monolayer selectively assembled on the second dielectric point material.

8 .- 12 . (canceled)

Assignees

• IBM

Inventors

• Cao Qing
• Cheng Kangguo
• Li Zhengwen
• Liu Fei
• Zhang Zhen

Classifications

• Y10S977/742

  Carbon nanotubes, CNTs · CPC title

• Y10S977/938

  Field effect transistors, FETS, with nanowire- or nanotube-channel region · CPC title

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• Y10S977/842

  for carbon nanotubes or fullerenes · CPC title