Technique for fabrication of microelectronic capacitors and resistors

Patent metadata

Field	Value
Publication number	US-2016293589-A1
Application number	US-201615175738-A
Country	US
Kind code	A1
Filing date	Jun 7, 2016
Priority date	Oct 31, 2013
Publication date	Oct 6, 2016
Grant date	—

Abstract

A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits.

First claim

What is claimed is:

1 . A method of making an integrated electronic structure, the method comprising:
forming an array of trenches in a dielectric block on a substrate, a first portion of the array including wide trenches having a wide trench width, and a second portion of the array including narrow trenches having a narrow trench width; preferentially lowering wall heights of the wide trenches relative to those of the narrow trenches; forming a first metal layer that fills the narrow trenches and partially fills the wide trenches, the first metal layer forming a metal serpentine resistor in a vertical orientation orthogonal to a plane of the substrate; covering the metal serpentine with a dielectric; preferentially thinning regions of the dielectric between the wide trenches; and filling the wide trenches with a second metal layer, the second metal layer together with the first metal layer and the dielectric forming a plurality of vertical and horizontal parallel plate capacitor antifuses, in the region of the wide trenches.

2 . The method of making an integrated electronic structure according to claim 1 , wherein preferentially lowering wall heights of the wide trenches relative to those of the narrow trenches is carried out without a masking step.

3 . The method of making an integrated electronic structure according to claim 1 , wherein preferentially thinning an insulator between the wide trenches is carried out without a masking step between the covering step and the filling step.

4 . The method of making an integrated electronic structure according to claim 3 , wherein preferentially thinning the insulator between the wide trenches includes polishing the insulator for a fixed process time.

5 . The method of making an integrated electronic structure according to claim 1 , wherein only two mask cycles are used from the forming an array of trenches step to the filling the wide trenches step.

6 . The method of making an integrated electronic structure according to claim 1 , wherein the narrow trenches are characterized by a high aspect ratio in which each narrow trench has a wall height that is at least six times greater than the narrow trench width.

7 . A method of forming thin and thick regions of an insulator without using a mask, the method comprising:
conformally depositing the insulator onto an irregular surface of a semiconductor substrate; and polishing the insulator for a fixed period of time.

8 . The method of claim 7 , wherein the irregular surface has a step height.

9 . The method of claim 7 , wherein the insulator is a silicon nitride carbide material.

Assignees

• IBM
• St Microelectronics Inc

Inventors

• Zhang John H
• Clevenger Lawrence A
• Radens Carl
• Xu Yiheng
• Wornyo Edem

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/493

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title