Semiconductor devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016293552-A1
Application number	US-201615048998-A
Country	US
Kind code	A1
Filing date	Feb 19, 2016
Priority date	Mar 30, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

A semiconductor device includes an insulating interlayer on a first region of a substrate. The insulating interlayer has a recess therein and includes a low-k material having porosity. A damage curing layer is formed on an inner surface of the recess. A barrier pattern is formed on the damage curing layer. A copper structure fills the recess and is disposed on the barrier pattern. The copper structure includes a copper pattern and a copper-manganese capping pattern covering a surface of the copper pattern. A diffusion of metal in a wiring structure of the semiconductor device may be prevented, and thus a resistance of the wiring structure may decrease.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
an insulating interlayer on a substrate, the insulating interlayer having a recess therein and including a low-k material having porosity; a damage curing layer on an inner surface of the recess; a barrier pattern on the damage curing layer; and a copper structure filling the recess having the barrier pattern therein, the copper structure including a copper pattern and a copper-manganese capping pattern covering a surface of the copper pattern.

2 . The semiconductor device of claim 1 , wherein the insulating interlayer includes Si—O bonds, and some oxygen atoms of the Si—O bonds in the insulating interlayer are substituted by a methyl group (CH 3 ).

3 . The semiconductor device of claim 1 , wherein the damage curing layer has a porosity lower than a porosity of the insulating interlayer.

4 . The semiconductor device of claim 1 , wherein the damage curing layer includes an insulating material having Si—C bonds, and a density of the Si—C bonds in the damage curing layer is higher than a density of Si—C bonds in the insulating interlayer.

5 . The semiconductor device of claim 1 , wherein a portion of the barrier pattern on a sidewall of the recess has a thickness less than a thickness of a portion of the barrier pattern on a bottom of the recess.

6 . The semiconductor device of claim 1 , wherein the copper-manganese capping pattern has a thickness of about 0.1 nm to about 10 nm

7 . The semiconductor device of claim 1 , wherein a portion of the copper-manganese capping pattern on an upper central portion of the copper pattern has a first thickness, and a portion of the copper-manganese capping pattern on an upper edge portion of the copper pattern has a second thickness greater than the first thickness.

8 . The semiconductor device of claim 1 , wherein the copper-manganese capping pattern is formed on an upper surface of the copper pattern.

9 . The semiconductor device of claim 1 , wherein the copper-manganese capping pattern is formed on an upper surface and a sidewall of the copper pattern.

10 . The semiconductor device of claim 9 , wherein an amount of manganese in a portion of the copper-manganese capping pattern on the sidewall of the copper pattern is less than an amount of manganese in a portion of the copper-manganese capping pattern on the upper surface of the copper pattern.

11 . A semiconductor device, comprising:
an insulating interlayer having a recess on a substrate, the insulating interlayer including a low-k material having porosity; a barrier pattern on a sidewall and a bottom of the recess, a portion of the barrier layer on a sidewall of the recess having a thickness less than a thickness of a portion of the barrier layer on a bottom of the recess; and a copper structure filling the recess having the barrier pattern therein, the copper structure including a copper pattern and a copper-manganese capping pattern covering a surface of the copper pattern.

12 . The semiconductor device of claim 11 , wherein the copper pattern includes manganese of 0.005 wt % to 5 wt %, and the copper-manganese capping pattern includes manganese having a weight percentage higher than a weight percentage of manganese in the copper pattern.

13 . The semiconductor device of claim 12 , wherein the copper-manganese capping pattern includes manganese of 0.1 wt % to 80 wt %.

14 . The semiconductor device of claim 11 , wherein the copper-manganese capping pattern is formed on an upper surface, a sidewall and a bottom of the copper pattern, and wherein a portion of the copper-manganese capping pattern on an upper central portion of the copper pattern has a first thickness, and a portion of the copper-manganese capping pattern on an upper edge portion of the copper pattern has a second thickness greater than the first thickness.

15 . The semiconductor device of claim 11 , further comprising a damage curing layer between the barrier pattern and the insulating interlayer, the damage curing layer having a porosity lower than a porosity of the insulating interlayer.

16 . A semiconductor device, comprising:
a first insulating interlayer on a substrate, the first insulating interlayer having a via hole therethrough; a second insulating interlayer including a low-k material having porosity and having a trench therethrough, the trench being in communication with the via hole and extending in a first direction; a damage curing layer on inner surfaces of the via hole and the trench; a barrier pattern on the damage curing layer; and a copper structure on the barrier layer to fill the via hole and the trench, the copper structure including a copper pattern and a copper-manganese capping pattern covering a surface of the copper pattern.

17 . The semiconductor device of claim 16 , wherein the damage curing layer has a porosity lower than porosities of the first and second insulating interlayers.

18 . The semiconductor device of claim 16 , wherein the damage curing layer includes an insulating material having Si—C bonds, and a density of the Si—C bonds in the damage curing layer is higher than a density of Si—C bonds in each of the first and second insulating interlayers.

19 . The semiconductor device of claim 16 , wherein the copper-manganese capping pattern has a thickness of about 0.1 nm to about 10 nm

20 . The semiconductor device of claim 16 , wherein a portion of the copper-manganese capping pattern on an upper central portion of the copper pattern has a first thickness, and a portion of the copper-manganese capping layer pattern on an upper edge portion of the copper layer pattern has a second thickness greater than the first thickness.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yim Tae-Jin
• Ahn Sang-Hoon
• Oszinda Thomas
• Baek Jong-Min
• Kim Byung Hee
• Lee Nae-In
• Jun Kee-Young

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/096

  by contacting with gases, liquids or plasmas · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/055

  by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title