Integrated cantilever switch

US2016293371A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016293371-A1
Application numberUS-201514675359-A
CountryUS
Kind codeA1
Filing dateMar 31, 2015
Priority dateMar 31, 2015
Publication dateOct 6, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm 2 .

First claim

Opening claim text (preview).

1 . An apparatus, comprising: a silicon substrate; a layered stack overlying the silicon substrate, the layered stack including an epitaxial semiconductor layer; a cavity positioned within the layered stack; a flexible member extending from the epitaxial semiconductor layer of the layered stack into the cavity; and a gate overlying the flexible member, the gate configured to control motion of the flexible member via an electric signal. 2 . The apparatus of claim 1 wherein the gate is configured to control the motion by one or more of a capacitive mechanism, an electrostatic mechanism, or induction. 3 . The apparatus of claim 1 wherein the cavity extends underneath a portion of the gate. 4 . The apparatus of claim 1 wherein the flexible member is a cantilever arm, and the gate is configured to deflect the cantilever arm. 5 . The apparatus of claim 4 wherein the cantilever arm has an aspect ratio greater than 4.0. 6 . The apparatus of claim 4 wherein the cantilever arm is conductive and, when deflected, makes contact with a current-carrying portion of the layered stack, thus closing a switch. 7 . The apparatus of claim 6 wherein the gate is a transistor gate and closing the switch permits current to flow between source and drain terminals of a transistor. 8 . A switch, comprising: a silicon substrate; a gate electrode overlying the silicon substrate, the gate electrode configured to receive a voltage applied to activate the switch; and a flexible member having a metal tip, the flexible member disposed within a cavity between the silicon substrate and the gate electrode, the metal tip configured to deflect in response to the applied voltage, so as to close the switch. 9 . The switch of claim 8 , further comprising a source region and a drain region formed on the silicon substrate, wherein the switch is a type of transistor. 10 . An integrated circuit that includes the transistor of claim 9 . 11 . The switch of claim 8 , further comprising a buried oxide layer within the silicon substrate and a backside electrical contact to the silicon substrate. 12 . The switch of claim 8 , further comprising a doped epitaxial semiconductor adjacent to the gate electrode, the doped epitaxial semiconductor configured to make contact with the flexible member when a voltage is applied to the gate electrode. 13 . (canceled) 14 . The switch of claim 8 , having a footprint within a range of 0.1×0.1 μm 2 -100×100 μm 2 . 15 .- 23 . (canceled) 24 . A device, comprising: a silicon substrate; a layered stack on the silicon substrate, the layered stack including first and second epitaxial semiconducting materials in an alternating arrangement; and a moveable member having an end that extends from the second epitaxial semiconducting material into a cavity; a transistor gate structure overlying the moveable member; a raised source region spaced apart from the transistor gate structure by an insulating material; and a raised drain region spaced apart from the transistor gate structure by the insulating material. 25 . The device of claim 24 wherein the raised source and drain regions are faceted. 26 . The device of claim 24 wherein the moveable member is a cantilever arm. 27 . The device of claim 24 wherein the insulating material is a spin-on glass material. 28 . The device of claim 24 wherein the transistor gate structure includes a metal gate, a high-k gate dielectric, and insulating sidewall spacers. 29 . The device of claim 24 wherein the epitaxial semiconducting materials include one or more of silicon and silicon germanium. 30 . The device of claim 24 wherein the silicon substrate is a silicon-on-insulator substrate that includes a buried oxide layer. 31 . The device of claim 24 , further comprising a metal tip on the end of the moveable member.

Assignees

Inventors

Classifications

  • Anisotropic liquid etching (H10P50/61 takes precedence) · CPC title

  • Silicon, silicon germanium or germanium · CPC title

  • Apparatus or processes specially adapted to the manufacture of relays or parts thereof · CPC title

  • using micromechanics · CPC title

  • making use of micromechanics · CPC title

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What does patent US2016293371A1 cover?
An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneat…
Who is the assignee on this patent?
St Microelectronics Inc
What technology area does this patent fall under?
Primary CPC classification H01H59/0009. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Oct 06 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).