Semiconductor memory device and method of operating the same
US-2016254043-A1 · Sep 1, 2016 · US
Semiconductor memory device
US2016293243A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016293243-A1 |
| Application number | US-201514854990-A |
| Country | US |
| Kind code | A1 |
| Filing date | Sep 15, 2015 |
| Priority date | Apr 6, 2015 |
| Publication date | Oct 6, 2016 |
| Grant date | — |
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Abstract
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A semiconductor memory device may include a memory bank having a plurality of word lines arranged at a predetermined address interval, an address latching unit suitable for storing a target address corresponding to a target word line of the plurality of word lines, and a refresh control unit suitable for performing a refresh operation on first to Nth word lines having different address intervals from the target word line based on the target address in response to a smart refresh command, wherein N is a natural number.
First claim
Opening claim text (preview).
What is claimed is: 1 . A semiconductor memory device, comprising: a memory bank having a plurality of word lines arranged at a predetermined address interval; an address latching unit suitable for storing a target address corresponding to a target word line of the plurality of word lines; and a refresh control unit suitable for performing a refresh operation on first to Nth word lines having different address intervals from the target word line based on the target address i…
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Physics · mapped topic
Physics · mapped topic
- G11C29/783Primary
Physics · mapped topic
- G11C11/406Primary
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US2016293243A1 cover?
- A semiconductor memory device may include a memory bank having a plurality of word lines arranged at a predetermined address interval, an address latching unit suitable for storing a target address corresponding to a target word line of the plurality of word lines, and a refresh control unit suitable for performing a refresh operation on first to Nth word lines having different address interval…
- Who is the assignee on this patent?
- Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification G11C29/783. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Thu Oct 06 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).