Systems, methods, and apparatuses for performing refresh operations

Patent metadata

Field	Value
Publication number	US-2016293242-A1
Application number	US-201514675149-A
Country	US
Kind code	A1
Filing date	Mar 31, 2015
Priority date	Mar 31, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

Methods, apparatuses, and systems for performing refresh operations on a memory cell array that does not have an Nth-power-of-2 number of memory mats are disclosed. An address counter configured to skip the refresh addresses not assigned to a memory mat is disclosed. An address counter configured to distribute the refresh addresses not assigned to a memory mat across a refresh period is disclosed. A mask determination circuit that suppresses refresh operations for refresh addresses not assigned to a memory mat is disclosed.

First claim

1 . An apparatus, comprising:
an address counter configured to provide refresh addresses to a refresh circuit, wherein the address counter includes:
a plurality of counter cells configured to count through count values between a minimum count value to a maximum count value, wherein an output of each of the plurality of counter cells each corresponds to an address bit of the refresh address; and
a reset circuit coupled to a counter cell of the plurality of counter cells, wherein the reset circuit is configured to reset the counter cell of the plurality of counter cells to an initial value responsive to the plurality of counter cells changing from a first count value to a second count value to skip at least some of the count values to provide the refresh addresses, wherein the first and second count values are less than the maximum count value.

2 . The apparatus of claim 1 , wherein the reset circuit is coupled to two counter cells of the plurality of counter cells, and the first count value includes one of the two counter cells of the plurality of counter cells set to 1 and the other one of the two counter cells of the plurality of counter cells set to 0, and wherein the second count value includes the two counter cells of the plurality of counter cells set to 1.

3 . The apparatus of claim 1 , wherein the initial value includes all of the at least two counter cells set to 0.

4 . The apparatus of claim 1 , wherein the counter cell of the plurality of counter cells provides an output that corresponds to the most significant bit of the refresh address.

5 . The apparatus of claim 1 , wherein the reset circuit is coupled to two counter cells of the plurality of counter cells, and the two counter cells of the plurality of counter cells provide outputs that correspond to consecutive bits of the refresh address.

6 . The apparatus of claim 1 , wherein the reset circuit is coupled to two counter cells of the plurality of counter cells and the reset circuit comprises:
a NAND gate configured to receive the outputs of the two counter cells of the plurality of counter cells; and an AND gate configured to receive an output of the NAND gate and an address counter reset signal as inputs, wherein the AND gate is further configured to provide an output to the two counter cells of the plurality of counter cells.

7 . The apparatus of claim 6 , wherein the reset circuit further comprises a delay circuit coupled to the output of the NAND gate and an input of the AND gate, wherein the delay circuit is configurable to provide a delay of a desired period.

8 . An apparatus, comprising:
an address counter configured to provide a refresh address to a refresh circuit, wherein the address counter includes a plurality of counter cells coupled in series from a first counter cell to a last counter cell downstream of the first counter cell, wherein an output of each of the plurality of counter cells each correspond to an address bit of the refresh address, wherein the address bit of the refresh address provided by a later counter cell downstream of an earlier counter cell is a less significant bit of the refresh address than the address bit of the refresh address provided by the earlier counter cell.

9 . The apparatus of claim 8 , wherein a second counter cell downstream of the later counter cell provides an address bit of the refresh address that is a less significant than the address bit of the refresh address provided by the earlier counter cell.

10 . The apparatus of claim 8 , wherein the address bit of the refresh address provided by the later counter cell and the address bit of the refresh address provided by the earlier counter cell are consecutive bits of the refresh address.

11 . The apparatus of claim 8 , wherein one of the address bit of the refresh address provided by the later counter cell and the address bit of the refresh address provided by the earlier counter cell is a most significant bit of the refresh address.

12 . The apparatus of claim 8 , wherein the address counter is a binary counter.

13 . The apparatus of claim 8 , wherein the refresh circuit refreshes memory blocks in a memory at non-consecutive memory addresses, responsive to the refresh address.

14 . The apparatus of claim 13 , wherein at least one refresh address does not correspond to a memory address of the memory.

15 . An apparatus, comprising:
an address counter configured to provide a refresh address; a refresh circuit configured to perform a refresh operation on memory blocks in a memory based, at least in part, on the refresh address; and a mask determination circuit configured to receive the refresh address, wherein the mask determination circuit is further configured to suppress the refresh operation when the refresh address does not correspond to a memory address in the memory.

16 . The apparatus of claim 15 , wherein the mask determination circuit includes:
an address decoder configured to decode the refresh address; and a comparison circuit configured to receive a decoded refresh address corresponding to a plurality of segments and a segment mask signal from a mask information storage circuit; wherein the comparison circuit is configured to compare each of the plurality of segments to a corresponding segment of the segment mask signal and suppress the refresh operation when the plurality of segments matches the segment mask signal; wherein at least one of the corresponding segments of the segment mask signal is fixed to a high logic level.

17 . The apparatus of claim 16 , wherein the at least one of the corresponding segments of the segment mask signal corresponds to the most significant bit of the refresh address.

18 . The apparatus of claim 16 , wherein at least two of the corresponding segments of the segment mask signal is fixed to a high logic level.

19 . The apparatus of claim 18 , wherein the at least two of the corresponding segments of the segment mask signal are consecutive segments.

20 . A method, comprising:
incrementing a count value of an address counter from a minimum count value to a maximum count value; providing a refresh address from the address counter for the count value; and resetting an address bit of the address counter to a first count value responsive to the address counter having a second count value, wherein the second count value is less than the maximum count value.

21 . The method of claim 20 , further comprising refreshing a block of memory at a memory address when the refresh address corresponds to the memory address.

22 . The method of claim 20 , wherein the address counter is incremented responsive to a clock signal.

23 . The method of claim 20 , wherein the first and second count values are different.

24 . A method, comprising:
incrementing an address counter; providing a refresh address from the address counter for each increment, wherein at least one bit of the refresh address is transposed with at least one other bit of the refresh address; and refreshing a block of memory at a memory address when the refresh address corresponds to the memory address, wherein the blocks of memory are refreshed non-consecutively.

25 . The method of claim 24 , wherein the address counter includes a plurality of counter cells, wherein the output of each counter cell corresponds to a bit of the refresh address.

26 . The method of claim 24 , wherein the address counter

Assignees

• Micron Technology Inc

Inventors

• Nakamura Takaaki
• Saso Kazuya

Classifications

• G11C11/40622 Primary

  Partial refresh of memory arrays · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C11/406 Primary

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• G11C11/40615 Primary

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title