Packet processing system, method and device having reduced static power consumption

Patent metadata

Field	Value
Publication number	US-2016292079-A1
Application number	US-201514673819-A
Country	US
Kind code	A1
Filing date	Mar 30, 2015
Priority date	Mar 30, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

A buffer logic unit of a packet processing device including a power gate controller. The buffer logic unit for organizing and/or allocating available pages to packets for storing the packet data based on which of a plurality of separately accessible physical memories that pages are associated with. As a result, the power gate controller is able to more efficiently cut off power from one or more of the physical memories.

First claim

We claim:

1 . A packet processing system comprising:
a non-transitory computer-readable packet memory comprising a plurality of physical memory units logically divided into one or more pools and able to be independently read from or written to, wherein each of the pools is divided into a plurality of pages such that each of the pages define a separate portion of the physical memory units of the pool; a non-transitory computer-readable buffer memory comprising a separate page buffer for each of the pools, wherein each of the page buffers is filled with one or more of the pages of the associated pool; and a buffer memory logic coupled with the buffer memory, wherein for each portion of packet data that needs to be stored, the buffer memory logic is configured to:
allocate the page that was last added within one of the page buffers to store the portion of the packet data;
remove the allocated page from the one of the page buffers while the portion of the packet data is stored on the portion of the physical memory units defined by the allocated page; and
add the allocated page back into the one of the page buffers when the portion of the packet data is no longer stored on the physical memory units defined by the allocated page.

2 . The system of claim 1 , wherein packet data of incoming packets is stored on the physical memory units at the separate portions of the memory units based on the pages.

3 . The system of claim 2 , wherein the buffer memory logic initially fills each of the page buffers with all of the pages of the associated pool such that the pages are grouped according to which of the physical memory units that the pages define the portion of.

4 . The system of claim 3 , further comprising a power gate controller coupled with the buffer memory and each of the physical memory units, wherein the power gate controller is configured to cut power to one or more of the physical memory units at times when all of the pages defining the portions of the one or more of the physical memory units are currently unallocated.

5 . The system of claim 4 , wherein:
the buffer memory comprises a separate page state table for each of the page buffers such that each of the page state tables is paired with a different one of the page buffers and for each of the pair; each entry of each of the state tables is associated with a different page of the pages of the page buffer that is paired with the state table of the entry; and page state data of each of the allocated pages is stored in the entry associated with the page until the allocated page is no longer allocated.

6 . The system of claim 5 , wherein the pages that define portions of the same physical memory unit form a set, wherein the entries that are associated with those pages form a group, wherein each of the groups of entries of each of the state tables are stored on separate clusters of one or more additional physical memory units of the buffer memory, and further wherein the power gate controller is configured to cut power to one or more of the clusters of the additional physical memory units at times when the sets of pages associated with the groups of the entries stored on the one or more of the clusters are unallocated.

7 . The system of claim 6 , wherein the buffer memory comprises a counter for each of the sets of pages, wherein the counter indicates a number of the pages of the set that are currently allocated.

8 . The system of claim 7 , wherein the page state data comprises one or more of a pointer to a next page used to store a packet, a start of the packet indicator, an end of the packet indicator, a byte count, errors incurred and a number of references.

9 . The system of claim 8 , wherein each of the pools comprise a plurality of memory banks.

10 . A packet processing system comprising:
a non-transitory computer-readable packet memory comprising a plurality of physical memory units logically divided into one or more pools and able to be independently read from or written to, wherein the physical memory units of each of the pool are ranked within a memory ranking respect to each other, wherein each of the pools is divided into a plurality of pages such that each of the pages define a separate portion of the physical memory units of the pool; a non-transitory computer-readable buffer memory comprising a separate page buffer for each of the pools, wherein each of the page buffers is filled with one or more of the pages of the associated pool; and a buffer memory logic coupled with the buffer memory, wherein for each portion of packet data that needs to be stored, the buffer memory logic is configured to:
select one of the pools;
determine a number of the physical memory units of the selected pool that include a portion that is defined by at least one unallocated page of the pages of the page buffer associated with the selected pool;
determine which of the number of physical memory unit is ranked highest within the memory ranking for the selected pool;
allocate one of the at least one unallocated page of the physical memory unit that is ranked highest to store the portion of the packet data;
remove the allocated page from the one of the page buffers while the portion of the packet data is stored on the portion of the physical memory unit that is ranked highest defined by the allocated page; and
add the allocated page back into the one of the page buffers when the portion of the packet data is no longer stored on the portion of the physical memory unit that is ranked highest defined by the allocated page.

11 . The system of claim 10 , wherein packet data of incoming packets is stored on the physical memory units at the separate portions of the memory units based on the pages.

12 . The system of claim 11 , further comprising a power gate controller coupled with the buffer memory and each of the physical memory units, wherein the power gate controller is configured to cut power to one or more of the physical memory units at times when all of the pages defining the portions of the one or more of the physical memory units are currently unallocated.

13 . The system of claim 12 , wherein:
the buffer memory comprises a separate page state table for each of the page buffers such that each of the page state tables is paired with a different one of the page buffers; each entry of each of the state tables is associated with a different page of the pages of the page buffer that is paired with the state table of the entry; and page state data of each of the allocated pages is stored in the entry associated with the page until the allocated page is no longer allocated.

14 . The system of claim 13 , wherein the pages that define portions of the same physical memory unit form a set, wherein the entries that are associated with those pages form a group, wherein each of the groups of entries of each of the state tables are stored on separate clusters of one or more additional physical memory units of the buffer memory, and further wherein the power gate controller is configured to cut power to one or more of the clusters of the additional physical memory units at times when the sets of pages associated with the groups of the entries stored on the one or more of the clusters are unallocated.

15 . The system of claim 14 , wherein the buffer memory comprising a counter for each of the sets of pages, wherein the counter indicates a number of the pages of the set that are currently allocated.

16 . The system of claim 15 , wherein the page state data comprises one or more of a pointer to a next page used to store a packe

Assignees

• Xpliant Inc

Inventors

• Musoll Enrique

Classifications

• H04L49/9047 Primary

  including multiple buffers, e.g. buffer pools · CPC title

• H04L67/1008

  based on parameters of servers, e.g. available memory or workload (monitoring of computer activity G06F11/30) · CPC title

• H04L2012/5631

  Resource management and allocation · CPC title

• G06F3/0647

  Migration mechanisms · CPC title

• G06F12/0895 Primary

  of parts of caches, e.g. directory or tag array · CPC title