Method and apparatus for a superscalar processor

Patent metadata

Field	Value
Publication number	US-2016291980-A1
Application number	US-201514676461-A
Country	US
Kind code	A1
Filing date	Apr 1, 2015
Priority date	Apr 1, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

A superscalar processor, for out of order self-timed execution, comprising a plurality of independent self-timed function units, having corresponding instruction queues for holding instructions to be executed by the function unit. The processor further comprising an instruction dispatcher configured for inputting instructions in program counter order; and determining an appropriate function unit for execution of the instruction and a resource management unit configured for monitoring the function units and signaling availability of the appropriate function unit, wherein the dispatcher only dispatches the instruction to the appropriate function unit in response to the availability signal from the resource management unit.

First claim

1 . A super scalar processor comprising:
a plurality of parallel self-timed function units; an instruction dispatcher configured to dispatch instructions to function units in a program counter order; and event logic associated with each of the plurality of function units, the event logic configured to trigger operation of its associated function unit to generate an instruction execution result in response to receipt of a dispatched instruction at the function unit, where execution results among the plurality of parallel function units are unconstrained to be generated in program counter order.

2 . The processor of claim 1 , wherein the function units are interconnected to share execution results.

3 . The processor of claim 2 , including a data memory controller connected to read the execution results; and a plurality of load address FIFO queues each assigned to respective address generation function units.

4 . The processor of claim 3 , wherein the memory controller is configured to check if every load address conflicts with a pending store address.

5 . The processor of claim 3 , wherein a resource manager triggers a store address to the memory controller.

6 . The processor of claim 1 , wherein the instruction dispatcher is further configured to:
fetch instructions in program counter order; and determine a target execution unit for execution of a fetched instruction.

7 . The processor of claim 1 , further including a resource manager configured to:
monitor function units; and determine availability of target function units.

8 . The processor of claim 7 , wherein the resource manager is connected to control commitment of execution results.

9 . The processor of claim 8 , wherein the resource manager is self-clocked.

10 . The processor of claim 7 , wherein the instruction dispatcher is further configured to:
request from the resource manager, allocation of the target function unit; and only upon receipt of the allocation to dispatch the instruction to the target function unit.

11 . The processor of claim 7 , wherein the resource manager is further configured to flag the unavailability of the target function unit once it is allocated to an instruction.

12 . The processor of claim 11 , wherein the resource manager is further configured to unallocate an allocated function unit once the resource manager commits its execution result to a register file or memory.

13 . The processor of claim 12 , wherein the resource manager is configured to maintain a FIFO queue, wherein an earliest allocated function unit is at a head of the queue and a later allocated function unit is at a tail of the queue.

14 . The processor of claim 13 , wherein the FIFO queue comprises a plurality of subfields associated to an allocated function unit and wherein the subfields are in the same FIFO order as the allocated function units.

15 . The processor of claim 7 , wherein the resource manager is event triggered.

16 . The processor of claim 7 , wherein resource manager is self-clocked.

17 . The processor of claim 1 , wherein the instruction dispatcher includes a scoreboard for maintaining a history of dispatched instructions.

18 . The processor of claim 1 , wherein the function unit includes an instruction buffer and the instruction is dispatched to the instruction buffer of the target function unit.

19 . The processor of claim 1 , wherein the processor is implemented in a network element.

Assignees

• Huawei Tech Co Ltd

Inventors

• Ge Yiqun
• Shi Wuxian

Classifications

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/3836 Primary

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/3842

  Speculative instruction execution · CPC title

• G06F9/3824

  Operand accessing · CPC title

• G06F9/3557

  using program counter as base address · CPC title