Method of compiling program, storage medium, and apparatus

Patent metadata

Field	Value
Publication number	US-2016291975-A1
Application number	US-201615010089-A
Country	US
Kind code	A1
Filing date	Jan 29, 2016
Priority date	Mar 30, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

A method of compiling a program that executes a plurality of unit processes in parallel, the method includes: replacing a load instruction of a volatile variable, the volatile variable being a variable included in the program and having a possibility of being overwritten by another unit process, with a beginning load instruction indicating a beginning of a range of transactionization and a load, and an end instruction indicating an ending of the range of the transactionization; moving the beginning load instruction before a position of the load instruction of the volatile variable in the program by instruction scheduling; and generating a beginning instruction indicating a beginning of a range of the transactionization and a load instruction of the volatile variable from the moved beginning load instruction.

First claim

What is claimed is:

1 . A method of compiling a program that executes a plurality of unit processes in parallel, the method comprising:
replacing a load instruction of a volatile variable, the volatile variable being a variable included in the program and having a possibility of being overwritten by another unit process, with a beginning load instruction indicating a beginning of a range of transactionization and a load, and an end instruction indicating an ending of the range of the transactionization; moving the beginning load instruction before a position of the load instruction of the volatile variable in the program by instruction scheduling; and generating a beginning instruction indicating a beginning of a range of the transactionization and a load instruction of the volatile variable from the moved beginning load instruction.

2 . The method according to claim 1 , wherein
the moving moves the beginning load instruction to a preceding merge basic block.

3 . The method according to claim 1 , wherein
the moving moves the beginning load instruction to a beginning of a basic block.

4 . The method according to claim 1 , wherein
the moving moves the beginning load instruction such that a predetermined number of instructions are included between the beginning load instruction and the end instruction.

5 . The method according to claim 1 , wherein
the transactionization is executed by a hardware transactional memory.

6 . A non-transitory storage medium storing a compiling program for causing a computer to execute a process compiling a program that executes a plurality of unit processes in parallel, the process comprising:
replacing a load instruction of a volatile variable, the volatile variable being a variable included in the program and having a possibility of being overwritten by another unit process, with a beginning load instruction indicating a beginning of a range of transactionization and a load, and an end instruction indicating an ending of the range of the transactionization; moving the beginning load instruction before a position of the load instruction of the volatile variable in the program by instruction scheduling; and generating a beginning instruction indicating a beginning of a range of the transactionization and a load instruction of the volatile variable from the moved beginning load instruction.

7 . The non-transitory storage medium according to claim 6 , wherein
the moving moves the beginning load instruction to a preceding merge basic block.

8 . The non-transitory storage medium according to claim 6 , wherein
the moving moves the beginning load instruction to a beginning of a basic block.

9 . The non-transitory storage medium according to claim 1 , wherein
the moving moves the beginning load instruction such that a predetermined number of instructions are included between the beginning load instruction and the end instruction.

10 . The non-transitory storage medium according to claim 1 , wherein
the transactionization is executed by a hardware transactional memory.

11 . An apparatus comprising:
a memory configured to store a program that executes a plurality of unit processes in parallel as a target for compiling; and a processor coupled to the memory and configured to:
replace a load instruction of a volatile variable, the volatile variable being a variable included in the program and having a possibility of being overwritten by another unit process, with a beginning load instruction indicating a beginning of a range of transactionization and a load, and an end instruction indicating an ending of the range of the transactionization;
move the beginning load instruction before a position of the load instruction of the volatile variable in the program by instruction scheduling; and
generate a beginning instruction indicating a beginning of a range of the transactionization and a load instruction of the volatile variable from the moved beginning load instruction.

12 . The apparatus according to claim 11 , wherein the processor is configured to move the beginning load instruction to a preceding merge basic block.

13 . The apparatus according to claim 11 , wherein the processor is configured to move the beginning load instruction to a beginning of a basic block.

14 . The apparatus according to claim 11 , wherein the processor is configured to move the beginning load instruction such that a predetermined number of instructions are included between the beginning load instruction and the end instruction.

15 . The apparatus according to claim 11 , wherein
the transactionization is executed by a hardware transactional memory.

Assignees

• Fujitsu Ltd

Inventors

• Hashida Takushi
• Nakamura Minoru
• Kawaba Motoyuki

Classifications

• G06F9/30032 Primary

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F8/453

  Data distribution · CPC title

• G06F9/30087 Primary

  Synchronisation or serialisation instructions · CPC title

• G06F9/30047

  Prefetch instructions; cache control instructions · CPC title

• G06F8/456

  Parallelism detection · CPC title