Array substrate, touch display panel and touch display device

US2016291749A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016291749-A1
Application numberUS-201514788688-A
CountryUS
Kind codeA1
Filing dateJun 30, 2015
Priority dateApr 1, 2015
Publication dateOct 6, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

One inventive aspect is an array substrate. The array substrate includes a plurality of touch leads, a common electrode layer, and a drive circuit. The common electrode layer is divided into a plurality of self-capacitive electrodes, and the self-capacitive electrodes are electronically connected to the drive circuit through the touch leads. The array substrate also includes a plurality of pixel units. Each touch lead is electronically connected to the self-capacitive electrode corresponding to the touch lead via a first via hole. At least one touch lead is continuous and passes through a whole column of the self-capacitive electrodes. In a direction perpendicular to the array substrate, a projection of the self-capacitive electrode covers projections of a plurality of pixel units. In addition, along a direction of the touch leads, an interval between two adjacent first via holes is greater than or equal to a length of two pixel units.

First claim

Opening claim text (preview).

What is claimed is: 1 . An array substrate, comprising: a plurality of touch leads; a common electrode layer; a drive circuit, wherein the common electrode layer is divided into a plurality of self-capacitive electrodes, and wherein the self-capacitive electrodes are electronically connected to the drive circuit through the touch leads; and a plurality of pixel units, wherein each touch lead is electronically connected to the self-capacitive electrode corresponding to the touch lead via a first via hole, wherein at least one of the touch leads is continuous and passes through a whole column of the self-capacitive electrodes, wherein, in a direction perpendicular to the array substrate, a projection of the self-capacitive electrode covers projections of a plurality of pixel units, and wherein, along a direction of the touch leads, an interval between two adjacent first via holes is greater than or equal to a length of two pixel units. 2 . The array substrate according to claim 1 , wherein the first via holes corresponding to two adjacent touch leads are in a staggered arrangement. 3 . The array substrate according to claim 1 , wherein the touch leads are all continuous and pass through the whole column of the self-capacitive electrodes. 4 . The array substrate according to claim 1 , further comprising a plurality of auxiliary electrode lines which are electronically connected to the self-capacitive electrodes via second via holes, wherein in the direction perpendicular to the array substrate, projections of the auxiliary electrode lines on different self-capacitive electrodes are line segments separated from each other. 5 . The array substrate according to claim 4 , wherein, in the direction perpendicular to the array substrate, projections of two adjacent second via holes electronically connected to a same auxiliary electrode line are separated by a projection of at least two pixel units. 6 . The array substrate according to claim 4 , wherein the first via holes and the second via holes are distributed uniformly on the self-capacitive electrodes. 7 . The array substrate according to claim 6 , wherein the auxiliary electrode lines are distributed uniformly on the self-capacitive electrodes, and wherein the touch leads are distributed uniformly between the auxiliary electrode lines. 8 . The array substrate according to claim 1 , further comprising a plurality of pixel electrodes, wherein the touch leads are in a same layer as the pixel electrodes. 9 . The array substrate according to claim 8 , wherein: A) the pixel electrodes are between the common electrode layer and a substrate of the array substrate; or B) the common electrode layer is between the pixel electrodes and a substrate of the array substrate. 10 . The array substrate according to claim 5 , wherein, in the direction perpendicular to the array substrate, projections of two adjacent first via holes electronically connected to a same touch lead are separated by a projection of eight pixel units, and wherein, in the direction perpendicular to the array substrate, projections of two adjacent second via holes electronically connected to a same auxiliary electrode line are separated by the projection of eight pixel units. 11 . A touch display panel comprising an array substrate, wherein the array substrate comprises: a plurality of touch leads; a common electrode layer; a drive circuit, wherein the common electrode layer is divided into a plurality of self-capacitive electrodes, and wherein the self-capacitive electrodes are electronically connected to the drive circuit through the touch leads; and a plurality of pixel units, wherein each touch lead is electronically connected to the self-capacitive electrode corresponding to the touch lead via a first via hole, wherein at least one of the touch leads is continuous and passes through a whole column of the self-capacitive electrodes, wherein, in a direction perpendicular to the array substrate, a projection of the self-capacitive electrode covers projections of a plurality of pixel units, and wherein, along a direction of the touch leads, an interval between two adjacent first via holes is greater than or equal to a length of two pixel units. 12 . A touch display device comprising a touch display panel comprising an array substrate, wherein the array substrate comprises: a plurality of touch leads; a common electrode layer; a drive circuit, wherein the common electrode layer is divided into a plurality of self-capacitive electrodes, and wherein the self-capacitive electrodes are electronically connected to the drive circuit through the touch leads; and a plurality of pixel units, wherein each touch lead is electronically connected to the self-capacitive electrode corresponding to the touch lead via a first via hole, wherein at least one of the touch leads is continuous and passes through a whole column of the self-capacitive electrodes, wherein, in a direction perpendicular to the array substrate, a projection of the self-capacitive electrode covers projections of a plurality of pixel units, and wherein, along a direction of the touch leads, an interval between two adjacent first via holes is greater than or equal to a length of two pixel units. 13 . The array substrate according to claim 3 , further comprising a plurality of auxiliary electrode lines which are electronically connected to the self-capacitive electrodes via second via holes, wherein, in the direction perpendicular to the array substrate, projections of the auxiliary electrode lines on different self-capacitive electrodes are line segments separated from each other.

Assignees

Inventors

Classifications

  • by capacitive means · CPC title

  • Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate · CPC title

  • G06F3/0412Primary

    Digitisers structurally integrated in a display · CPC title

  • for fringe field switching [FFS] where the common electrode is not patterned · CPC title

  • having a patterned common electrode · CPC title

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What does patent US2016291749A1 cover?
One inventive aspect is an array substrate. The array substrate includes a plurality of touch leads, a common electrode layer, and a drive circuit. The common electrode layer is divided into a plurality of self-capacitive electrodes, and the self-capacitive electrodes are electronically connected to the drive circuit through the touch leads. The array substrate also includes a plurality of pixe…
Who is the assignee on this patent?
Shanghai Tianma Microelectronics Co Ltd, Tianma Microelectronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F3/0412. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Oct 06 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).