Microfabricated ultrasonic transducers and related apparatus and methods

Patent metadata

Field	Value
Publication number	US-2016290970-A1
Application number	US-201615178025-A
Country	US
Kind code	A1
Filing date	Jun 9, 2016
Priority date	Jul 14, 2014
Publication date	Oct 6, 2016
Grant date	—

Abstract

Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature.

First claim

What is claimed is:

1 . A capacitive micromachined ultrasonic transducer (CMUT) substrate, comprising:
a first wafer having a plurality of ultrasonic transducer cavities formed in a first thermal oxide layer; and a second wafer having a second thermal oxide layer, bonded to the first layer, defining an oxide-to-oxide bond that seals the plurality of cavities, the plurality of ultrasonic transducer cavities being at a pressure from about 1×10 −3 Torr to about 1×10 −5 Torr.

2 . The CMUT substrate of claim 1 , wherein at least one of the first wafer and the second wafer is a silicon-on-insulator (SOI) wafer.

3 . The CMUT substrate of claim 1 , wherein at least one of the first wafer and the second wafer is a bulk silicon wafer.

4 . The CMUT substrate of claim 1 , wherein the first wafer is a silicon-on-insulator (SOI) wafer, and the second wafer is a bulk silicon wafer.

5 . The CMUT substrate of claim 4 , wherein the second wafer includes a thinned bulk silicon wafer that comprises a bottom electrode for the ultrasonic transducer cavities.

6 . The CMUT substrate of claim 5 , wherein the first wafer includes an SOI layer that comprises a flexible membrane of the ultrasonic transducer cavities.

7 . The CMUT substrate of claim 6 , further comprising a plurality of isolation structures formed in the bottom electrode so as to electrically isolate sections of the bottom electrode corresponding to individual ultrasonic transducer cavities.

8 . The CMUT substrate of claim 7 , wherein the isolation structures extend through the thinned bulk silicon layer comprising the bottom electrode.

9 . The CMUT substrate of claim 8 , wherein the isolation structures comprise trenches within the thinned bulk silicon layer that are filled with an insulating layer.

10 . The CMUT substrate of claim 8 , wherein the bottom electrode comprises doped sections of the thinned bulk silicon layer and the isolation structures comprise undoped sections of the thinned bulk silicon layer.

Assignees

• Butterfly Network Inc

Inventors

• Rothberg Jonathan M
• Alie Susan A
• Fife Keith G
• Sanchez Nevada J
• Ralston Tyler S

Classifications

• H10W72/5453

  connecting between multiple bond pads on a chip, e.g. daisy chain · CPC title

• B81C1/00238

  Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure · CPC title

• B81B2201/0271

  Resonators; ultrasonic resonators · CPC title

• B06B1/0292 Primary

  Electrostatic transducers, e.g. electret-type · CPC title

• B81C2203/0792

  Forming interconnections between the electronic processing unit and the micromechanical structure · CPC title