Thin Film Encapsulation of Electrodes

Patent metadata

Field	Value
Publication number	US-2016289064-A1
Application number	US-201415104182-A
Country	US
Kind code	A1
Filing date	Dec 16, 2014
Priority date	Dec 19, 2013
Publication date	Oct 6, 2016
Grant date	—

Abstract

A method of fabricating encapsulated microelectromechanical system (MEMS) devices, comprising: providing a substrate having one or more MEMS devices formed thereon; depositing a sacrificial layer over the substrate and the one or more MEMS devices; patterning the sacrificial layer to define one or more cavities in the sacrificial layer and around the one or more MEMS devices; forming a cap layer over the sacrificial layer and the one or more cavities, the cap layer having one or more etch holes defined therein; removing the sacrificial layer by etching the sacrificial layer at least through the one or more etch holes; and depositing a sealing layer over the cap layer and the one or more etch holes to encapsulate the one or more MEMS devices, the substrate, and the cap layer.

First claim

What is claimed is:

1 . A method of fabricating encapsulated microelectromechanical system (MEMS) devices, comprising:
providing a substrate having one or more MEMS devices formed thereon; depositing a sacrificial layer over the substrate and the one or more MEMS devices; patterning the sacrificial layer to define one or more cavities in the sacrificial layer and around the one or more MEMS devices; forming a cap layer over the sacrificial layer and the one or more cavities, the cap layer having one or more etch holes defined therein; removing the sacrificial layer by etching the sacrificial layer at least through the one or more etch holes; depositing a sealing layer over the cap layer and the one or more etch holes to encapsulate the one or more MEMS devices, the substrate, and the cap layer, and patterning the sealing layer to expose a plurality of portions of the cap layer for electrical contact after the depositing step.

2 . The method in accordance with claim 1 , wherein the step of forming the cap layer to define one or more etch holes comprises:
electroplating the cap layer over the sacrificial layer and the one or more cavities; laying a photoresist layer over the cap layer; patterning the photoresist layer; etching through the photoresist layer; and removing the photoresist layer.

3 . The method in accordance with claim 2 , wherein the electroplating step comprises electroplating the cap layer to form a plurality of electrodes embedded in the encapsulated MEMS device.

4 . The method in accordance with claim 2 , wherein the step of electroplating comprises:
depositing a layer of Cu/Ti as a seed layer; and electroplating an Ni cap layer over the seed layer.

5 . The method in accordance with claim 1 , wherein the substrate is a low resistivity silicon wafer.

6 . The method in accordance with claim 1 , wherein the sacrificial layer comprises a dielectric material including plasma enhanced chemical vapour deposition (PECVD) oxide.

7 . The method in accordance with claim 1 , wherein the sealing layer comprises a dielectric material including PECVD oxide.

8 . The method in accordance with claim 7 , wherein the one or more cavities patterned in the sacrificial layer and around the one or more MEMS devices define the cap layer to comprise a plurality of metal plates and metal columns, wherein the plurality of metal plates and metal columns are separated by the sealing layer to form a plurality of electrodes and bond pads embedded in the encapsulated MEMS device.

9 . A device comprising:
a substrate; one or more MEMS devices formed thereon; a cap layer; and a sealing layer; wherein the one or more MEMS devices are encapsulated within the cap layer and the sealing layer, and wherein the sealing layer is patterned to expose a plurality of portions of the cap layer for electrical contact.

10 . The device in accordance with claim 9 , wherein the cap layer comprises a plurality of electrodes embedded in the device.

11 . The device in accordance with claim 9 , wherein the cap layer comprises a plurality of metal plates and metal columns, wherein the plurality of metal plates and metal columns are separated by the sealing layer to form a plurality of electrodes and bond pads embedded in the device.

12 . The device in accordance with claim 9 , wherein the cap layer is configured to transmit electric fields vertically to the one or more MEMS devices encapsulated in response to the sealing layer providing dielectric isolation to predetermined segments of the cap layer.

13 . The device in accordance with claim 9 , wherein the cap layer is configured to transmit electric fields laterally to the one or more MEMS devices encapsulated in response to a corresponding metal column of the cap layer in contact with each of the one or more MEMS devices.

14 . The device in accordance with claim 9 , wherein the cap layer comprises a Ni cap layer electroplated on a Cu/Ti seed layer.

15 . The device in accordance with claim 9 , wherein the substrate is a low resistivity silicon wafer.

16 . The device in accordance with claim 9 , wherein the sealing layer comprises a dielectric material including PECVD oxide.

Assignees

• Agency Science Tech & Res

Inventors

• Lee Jae-Wung
• Sharma Jaibir
• Singh Navab

Classifications

• H10W74/121 Primary

  by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• B81C2203/0154

  Moulding a cap over the MEMS device · CPC title

• B81C1/00825

  Protect against mechanical threats, e.g. against shocks, or residues (B81C1/00261 take precedence) · CPC title