Image Decoding Apparatus, Image Coding Apparatus, and Coded Data Transformation Apparatus

Patent metadata

Field	Value
Publication number	US-2016286235-A1
Application number	US-201615174648-A
Country	US
Kind code	A1
Filing date	Jun 6, 2016
Priority date	Dec 6, 2013
Publication date	Sep 29, 2016
Grant date	—

Abstract

A hierarchical image decoding apparatus, a hierarchical image coding apparatus, and a hierarchical coded data transformation apparatus where the hierarchical image decoding apparatus includes a parameter set decoder that decodes scale adjustment information, and a predictive image generator that generates a predictive image on the basis of the scale adjustment information, and the hierarchical image coding apparatus includes a parameter set encoder that encodes scale adjustment information, and the hierarchical coded data transformation apparatus includes a parameter set adjustor that transforms input hierarchically coded data based on inputted information of interest region, and adjusts scale adjustment information such that inter-layer scales derived from the hierarchically coded data before and after transformation coincide with each other.

First claim

What is claimed is:

1 . An image decoding apparatus that decodes coded data on a higher layer included in hierarchically coded data, and restores a decoded picture on the higher layer which is a target layer, comprising:
a hardware processor; and a non-transitory memory coupled to the hardware processor, wherein the hardware processor is configured to execute instructions in the non-transitory memory to perform the following operations:
decode a parameter set;
generate a predictive image through inter-layer prediction according to a decoded pixel of a picture on a reference layer;
decode scale adjustment information pertaining to the reference layer; and
derive a reference position on the reference layer corresponding to a pixel of the target layer, using an inter-layer scale derived based on the scale adjustment information.

2 . The image decoding apparatus according to claim 1 , wherein a virtual reference layer size difference is derived based on the scale adjustment information.

3 . The image decoding apparatus according to claim 2 , wherein a value of the inter-layer scale derived by the hardware processor is an approximate value of a ratio between a virtual reference layer correspondence region size and a virtual reference layer size, and wherein the virtual reference layer size is a sum of a reference layer picture size and the virtual reference layer size difference.

4 . The image decoding apparatus according to claim 3 , wherein when the scale adjustment information is not included in the parameter set, a value of the scale adjustment information is set by the hardware processor such that the virtual reference layer size and the reference layer picture size are coincided with each other.

5 . The image decoding apparatus according to claim 1 , wherein the decoded picture on the higher layer have a higher resolution than a decoded picture on the reference layer.

6 . The image decoding apparatus according to claim 1 , wherein the decoded picture on the higher layer have a higher frame rate than a decoded picture on the reference layer.

7 . The image decoding apparatus according to claim 1 , wherein the decoded picture on the higher layer have a higher image quality than a decoded picture on the reference layer.

8 . The image decoding apparatus according to claim 1 , wherein the reference position is represented in an accuracy that is less than a unit of pixels on the reference layer.

9 . The image decoding apparatus according to claim 1 , wherein the hardware processor is further configured to execute an interpolation filter process to generate a predictive pixel value of the pixel of the target layer, by receiving the reference position as an input.

10 . An image coding apparatus generating coded data on a higher layer from an input image, comprising:
a hardware processor; and a non-transitory memory coupled to the hardware processor, wherein the hardware processor is configured to execute instructions in the non-transitory memory to perform the following operations:
decode a parameter set;
generate a predictive image through inter-layer prediction according to a decoded pixel of a picture on a reference layer;
encode scale adjustment information;
derive a reference position corresponding to a decoded pixel of the target layer, using an inter-layer scale value derived from the scale adjustment information; and
derive a virtual reference layer size difference based on the scale adjustment information.

11 . The image coding apparatus according to claim 10 , wherein the value of the inter-layer scale derived by the hardware processor is an approximate value of a ratio between a virtual reference layer correspondence region size and a virtual reference layer size, and wherein the virtual reference layer size is a sum of a reference layer picture size and the virtual reference layer size difference.

12 . The image coding apparatus according to claim 11 , wherein when the scale adjustment information is not included in the parameter set, a value of the scale adjustment information is set by the hardware processor such that the virtual reference layer size and the reference layer picture size are coincided with each other.

13 . The image coding apparatus according to claim 10 , wherein a decoded picture on the higher layer have a higher resolution than the decoded picture on the reference layer.

14 . The image coding apparatus according to claim 10 , wherein a decoded picture on the higher layer have a higher frame rate than the decoded picture on the reference layer.

15 . The image coding apparatus according to claim 10 , wherein a decoded picture on the higher layer have a higher image quality than the decoded picture on the reference layer.

16 . The image coding apparatus according to claim 10 , wherein the reference position is represented in an accuracy that is less than a unit of pixels on the reference layer.

17 . The image coding apparatus according to claim 10 , wherein the hardware processor is further configured to execute an interpolation filter process to generate a predictive pixel value of the pixel of the target layer by receiving the reference position as an input.

18 . A hierarchical coded data transformation apparatus, comprising:
a hardware processor; and a non-transitory memory coupled to the hardware processor, wherein the hardware processor is configured to execute instructions in the non-transitory memory to perform the following operations:
transform input hierarchically coded data based on inputted information of interest region;
generate hierarchically coded data for the interest region;
output the generated hierarchically coded data for the interest region
adjust scale adjustment information such that inter-layer scales derived from the hierarchically coded data before and after transformation are coincided with each other.

Assignees

• Huawei Tech Co Ltd

Inventors

• Yamamoto Tomoyuki
• Ikai Tomohiro
• Tsukuba Takeshi

Classifications

• H04N19/182

  the unit being a pixel · CPC title

• H04N19/105 Primary

  Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction · CPC title

• H04N19/59 Primary

  involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution · CPC title

• H04N19/187

  the unit being a scalable video layer · CPC title

• H04N19/51

  Motion estimation or motion compensation · CPC title