Demodulating frequency shift keying modulated input signal

Patent metadata

Field	Value
Publication number	US-2016285658-A1
Application number	US-201514867014-A
Country	US
Kind code	A1
Filing date	Sep 28, 2015
Priority date	Mar 27, 2015
Publication date	Sep 29, 2016
Grant date	—

Abstract

A method of demodulating an FSK modulated input signal whose frequency varies between first and second frequencies. The input signal is delayed by a plurality of cycles, providing a second signal. A succession of phase reference signals having respective incrementally greater phase delays relative to the input signal are provided. Samples of the phase reference signals are taken at intervals determined by the second signal. A transition between the first and second frequencies is detected when the relative values of the samples of the phase reference signals remain constant during a plurality of intervals after varying. A high speed clock is not required to perform the demodulation.

First claim

1 . A method of demodulating a frequency shift keying (FSK) modulated input signal whose frequency varies between a first frequency and a second frequency, the method comprising:
providing first and second signals having a relative delay greater than a plurality of cycles of the lesser of the first and second frequencies; providing a succession of phase reference signals having respective incrementally greater phase delays relative to the first signal; providing samples of the phase reference signals at intervals determined by the second signal; and detecting a transition between the first and second frequencies when the relative values of the samples vary during a first plurality of intervals and then remain constant during a second plurality of intervals.

2 . The method of claim 1 , wherein the greatest phase delay relative to the first signal is at least one half cycle of the first signal.

3 . The method of claim 2 , wherein phase reference signals whose delay is greater than one half cycle of the first signal are excluded from the samples.

4 . The method of claim 1 , wherein the delay between the first and second signals includes a number of cycles of the signals such that the phases of a plurality of the phase reference signals invert relative to the second signal.

5 . A method of demodulating a frequency shift keying (FSK) modulated first signal whose frequency varies between at least a first frequency and a second frequency, the method comprising:
providing a second signal having a delay relative to the first signal greater than a plurality of cycles of the lesser of the first and second frequencies; providing a succession of phase reference signals having respective incrementally greater phase delays relative to the first signal; providing samples of the phase reference signals at intervals determined by the second signal; and detecting a transition between the first and second frequencies when the relative values of the samples vary during a first plurality of intervals and then remain constant during a second plurality of intervals.

6 . The method of claim 5 , wherein the greatest phase delay relative to the first signal is greater than one half cycle of the first signal.

7 . The method of claim 5 , wherein phase reference signals whose delay is greater than one half cycle of the first signal are excluded from the samples.

8 . The method of claim 5 , wherein the delay between the first and second signals includes a number of cycles of the signals such that the phases of a plurality of the phase reference signals invert relative to the second signal.

9 . A demodulator for demodulating a frequency shift keying (FSK) modulated input signal whose frequency varies between at least a first frequency and a second frequency, comprising:
a delay module for providing first and second signals having a relative delay greater than a plurality of cycles of the lesser of the first and second frequencies of the input signal; a phase shift module for providing a succession of phase reference signals having respective incrementally greater phase delays relative to the first signal; a sampling module for providing samples of the phase reference signals at intervals determined by the second signal; and a detector for detecting a transition between the first and second frequencies when the relative values of the samples vary during a first plurality of intervals and then remain constant during a second plurality of intervals.

10 . The demodulator of claim 9 , wherein the greatest phase delay relative to the first signal is greater than one half cycle of the first signal.

11 . The demodulator of claim 10 , further comprising a filter that excludes from the samples phase reference signals whose delay is greater than one half cycle of the first signal.

12 . The demodulator of claim 9 , wherein the delay between the first and second signals includes a number of cycles of the signals such that the phases of a plurality of the phase reference signals to invert relative to the second signal.

13 . The demodulator of claim 9 , wherein the phase shift module comprises:
a plurality of delay phase elements connected in series whose respective outputs have incrementally greater phases relative to the first signal; and a plurality of sampling elements for sampling respective outputs of the delay phase elements at the intervals determined by the second signal.

14 . The demodulator of claim 9 , wherein the delay module provides a delay of the second signal relative to the first signal as a defined lapse of time.

15 . A wireless communications receiver for receiving a FSK modulated input signal and including the demodulator of claim 9 for demodulating the input signal.

Assignees

• Freescale Semiconductor Inc

Inventors

• Sui Zhiling
• Chen Zhijun
• Cheng Zhihong
• Pan Jiangtao

Classifications

• H04W56/0045

  compensating for timing error by altering transmission time · CPC title

• H04L27/1563 Primary

  using transition or level detection · CPC title

• H04L27/16

  Frequency regulation arrangements · CPC title

• H04L7/0087

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title

• H04L27/14 Primary

  Demodulator circuits; Receiver circuits · CPC title