Methods to introduce sub-micrometer, symmetry-breaking surface corrugation to silicon substrates to increase light trapping

Patent metadata

Field	Value
Publication number	US-2016284886-A1
Application number	US-201415030039-A
Country	US
Kind code	A1
Filing date	Oct 17, 2014
Priority date	Oct 18, 2013
Publication date	Sep 29, 2016
Grant date	—

Abstract

Provided is a method for fabricating a nanopatterned surface. The method includes forming a mask on a substrate, patterning the substrate to include a plurality of symmetry-breaking surface corrugations, and removing the mask. The mask includes a pattern defined by mask material portions that cover first surface portions of the substrate and a plurality of mask space portions that expose second surface portions of the substrate, wherein the plurality of mask space portions are arranged in a lattice arrangement having a row and column, and the row is not oriented parallel to a [110] direction of the substrate. The patterning the substrate includes anisotropically removing portions of the substrate exposed by the plurality of spaces.

First claim

What is claimed is:

1 . A method for fabricating a nanopatterned surface, comprising:
forming a mask on a single crystal substrate, the mask comprising a pattern, wherein the pattern is defined by mask material portions that cover first surface portions of the substrate and a plurality of mask space portions that expose second surface portions of the substrate, wherein the plurality of mask space portions are arranged in a lattice arrangement having a row and column, and the row is not oriented parallel to a [110] direction of the substrate; patterning the substrate to comprise a plurality of symmetry-breaking surface corrugations by anisotropically removing portions of the substrate exposed by the plurality of mask spaces; and removing the mask.

2 . The method of claim 1 , wherein the mask space portions comprise etch windows arranged in the rows and columns.

3 . The method of claim 1 , wherein the mask material portions comprise a plurality of nanopillars comprising dielectric material, and wherein the nanopillars arranged in the rows and columns.

4 . The method of claim 1 , wherein anisotropically removing portions of the substrate comprises wet-etching the substrate exposed by the plurality of space portions.

5 . The method of claim 4 , wherein wet-etching comprises introducing at least a portion of the substrate with the mask into a wet-etchant solution at a dipping direction, wherein the dipping direction defined by at least one of a first rotation angle (DA1) relative to the substrate's [110] direction, and an inclination angle (DA2) relative to the dipping direction

6 . The method of claim 5 , wherein DA2 is selected from about 25 degrees to about 50 degrees.

7 . The method of claim 5 , wherein the introducing comprises changing at least one of DA1 and DA2 as the substrate is contacted by the wet-etchant solution.

8 . The method of claim 4 , wherein wet-etching comprises providing the at least a portion of the substrate with the mask in the wet-etchant solution at a dipping orientation, wherein the dipping orientation is defined by a surface normal (n) of the substrate which is inclined from the gravity direction by a polar angle (θ) and is rotated by an azimuthal angle (φ) about the axis parallel to gravity.

9 . The method of claim 8 , wherein the providing comprises changing at least one of θ and φ as the substrate is etched by the wet-etchant solution.

10 . The method of claim 1 , wherein the lattice comprises a square lattice, a rectangular lattice, triangular lattice, centered-rectangular lattice, or an oblique lattice.

11 . The method of claim 1 , wherein forming the mask comprises:
forming a dielectric layer on the substrate; forming an antireflection coating on the dielectric layer; forming a photoresist layer on the antireflection coating; and either (i) forming the plurality of spaces, wherein the plurality of spaces comprise a plurality of windows extending through each of the dielectric layer, the antireflection coating and the photoresist layer, or (ii) forming the mask material portions, wherein the mask material portions comprise a plurality of nanopillars that each comprise portions of each of the dielectric layer, the antireflection coating and the photoresist layer.

12 . The method of claim 11 , wherein forming the dielectric layer comprises oxidizing a surface of the substrate.

13 . The method of claim 11 , wherein the dielectric layer comprises a thermally grown dielectric layer.

14 . The method of claim 11 , wherein the dielectric layer comprises SiO 2 .

15 . The method of claim 11 , wherein forming the plurality of spaces comprises:
patterning the photoresist; patterning the antireflective coating; and patterning the dielectric layer.

16 . The method of claim 15 , wherein
patterning the photoresist comprises removing portions of the photoresist to form first portions of the plurality of windows, the first portions of the plurality of windows extending through the photoresist and exposing portions of the antireflection coating; wherein patterning the antireflective coating comprises removing exposed portions of the antireflective coating to form second portions of the plurality of windows, the second portions of the plurality of windows extending from the first portion of the plurality of etch windows and exposing portions of the dielectric layer; and wherein patterning the dielectric layer comprises removing exposed portions of the dielectric layer to form third portions of the plurality of windows, the third portions of the plurality of windows extending from the second portion of the plurality of windows and exposing portions of the substrate.

17 . The method of claim 15 , wherein at least one of the patterning the photoresist, patterning the antireflective coating, and patterning the dielectric layer comprises exposing the photoresist, antireflective coating, and exposing the dielectric layer, respectively, to first and second doses of interferometric lithography interference, the first dose of interfereometric lithography interference occurring at a first direction and the second dose of interfereometric lithography interference occurring at a second direction, different than the first direction relative to a preselected crystallographic orientation of the substrate.

18 . The method of claim 15 , wherein patterning the dielectric layer comprises reactive ion etching the dielectric layer in CHF3/O2 plasma.

19 . The method of claim 1 , wherein the row is oriented at a non-zero angle around the [001] axis of the substrate.

20 . The method of claim 1 , wherein the substrate comprises single crystal silicon (c-Si).

21 . The method of claim 1 , wherein the plurality of symmetry-breaking surface corrugations define an array of inverted nanopyramids that extend into the substrate.

22 . The method of claim 21 , wherein the inverted array of inverted nanopyramids are arranged to have a symmetry selected from at least one of C 4v , C 4 , C 2 , and C 1 .

23 . The method of claim 21 , wherein the anisotropic etching step leaves flat unetched areas between the inverted nanopyramids

24 . The method of claim 23 , further comprising etching the substrate isotropically.

25 . The method of claim 23 , wherein etching the substrate isotropically comprises exposing the substrate to a solution mixture of HNO 3 and HF.

26 . The method of claim 1 , wherein the plurality of symmetry-breaking surface corrugations comprise first ones of the plurality of symmetry-breaking surface corrugations having a first symmetry and a second ones of the plurality of symmetry-breaking surface corrugations having a second symmetry, wherein the first and second symmetries are different.

27 . The method of claim 26 , wherein the plurality of symmetry-breaking surface corrugations further comprise third ones of the plurality of the symmetry-breaking surface corrugations disposed between the first and second ones, and wherein the third ones provide a symmetry transition between the first symmetry and the second symmetry.

28 . The method of claim 1 , further comprising depositing at least one layer on the patterned substrate, wherein the at least one layer conforms to the symmetry-breaking surface corrugations of the patterned substrate and comprises second symmetry-breaking surface corrugations.

Assignees

• Stc Unm

Inventors

• Han Sang Eon
• Hoard Brittany R
• Han Sang M
• Ghosh Swapnadip

Classifications

• H03H9/145

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• Y02E10/547

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• G02B1/005

  made of photonic crystals or photonic band gap materials (photonic band-gap structures or photonic lattices in integrated optics G02B6/1225; photonic band-gap structures or photonic lattices in optical fibres G02B6/02295) · CPC title

• H03H9/25

  Constructional features of resonators using surface acoustic waves {(devices for manipulating acoustic surface waves in general G10K11/36)} · CPC title

• H03H9/10

  Mounting in enclosures {(constructional combinations of enclosure with electromechanical and other electronic elements H03H9/0538)} · CPC title