Semiconductor memory device and method for manufacturing the same

US2016284868A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016284868-A1
Application numberUS-201615064735-A
CountryUS
Kind codeA1
Filing dateMar 9, 2016
Priority dateMar 24, 2015
Publication dateSep 29, 2016
Grant date

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  1. Title

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A semiconductor memory device in an embodiment includes a semiconductor layer, a control gate electrode, an organic molecular layer provided between the semiconductor layer and the control gate electrode, and a first insulating layer provided between the organic molecular layer and the semiconductor layer, the first insulating layer having a first layer containing alkyl chains and a second layer containing siloxane, the second layer being provided between the first layer and the organic molecular layer.

First claim

Opening claim text (preview).

What is claimed is: 1 . A semiconductor memory device comprising: a semiconductor layer; a control gate electrode; an organic molecular layer provided between the semiconductor layer and the control gate electrode; and a first insulating layer provided between the organic molecular layer and the semiconductor layer, the first insulating layer having a first layer containing alkyl chains and a second layer containing siloxane, the second layer being provided between the first layer and the organic molecular layer. 2 . The device according to claim 1 , wherein carbon number of each of the alkyl chains is between 4 and 30 inclusive. 3 . The device according to claim 1 , wherein the first layer is a monomolecular film. 4 . The device according to claim 1 , further comprising an inorganic second insulating layer provided between the first insulating layer and the semiconductor layer. 5 . The device according to claim 1 , further comprising a third insulating layer between the organic molecular layer and the control gate electrode. 6 . The device according to claim 1 , wherein the first layer is chemically bonded to the semiconductor layer. 7 . The device according to claim 4 , wherein the first layer is chemically bonded to the second insulating layer. 8 . The device according to claim 1 , wherein the organic molecular layer has oxidation-reduction molecules. 9 . The device according to claim 1 , wherein the first insulating layer contains a structure formed by chemical bonding of a first precursor described by molecular formula (1) and a second precursor described by molecular formula (2): wherein X, Y are independently selected from among silyl ether, phosphoryl ether, alkoxy, carbonyl, and ether, n is an integer greater than 0, R 1 to R 4 are independently selected from hydrogen, oxygen, silicon, hydrocarbon, halogen, halogenated silane, alkoxy silane, and silyl ether, and m is an integer greater than 0. 10 . A semiconductor memory device comprising: a stacked body in which insulating layers and control gate electrodes are stacked alternately; a semiconductor layer facing at least one of the control gate electrodes; an organic molecular layer provided between the semiconductor layer and the at least one of the control gate electrodes; and a first insulating layer provided between the organic molecular layer and the semiconductor layer, the first insulating layer having a first layer containing alkyl chains and a second layer containing siloxane, the second layer being provided between the first layer and the organic molecular layer. 11 . The device according to claim 10 , wherein carbon number of each of the alkyl chains is between 4 and 30 inclusive. 12 . The device according to claim 10 , wherein the first layer is a monomolecular film. 13 . The device according to claim 10 , further comprising an inorganic second insulating layer provided between the first insulating layer and the semiconductor layer. 14 . The device according to claim 10 , further comprising a third insulating layer between the organic molecular layer and the at least one of the control gate electrodes. 15 . The device according to claim 10 , wherein the first layer is chemically bonded to the semiconductor layer. 16 . The device according to claim 13 , wherein the first layer is chemically bonded to the second insulating layer. 17 . The device according to claim 10 , wherein the organic molecular layer has oxidation-reduction molecules. 18 . The device according to claim 10 , wherein the first insulating layer contains a structure formed by chemical bonding of a first precursor described by molecular formula (1) and a second precursor described by molecular formula (2): wherein X, Y are independently selected from among silyl ether, phosphoryl ether, alkoxy, carbonyl, and ether, n is an integer greater than 0, R 1 to R 4 are independently selected from hydrogen, oxygen, silicon, hydrocarbon, halogen, halogenated silane, alkoxy silane, and silyl ether, and m is an integer greater than 0. 19 . A method for manufacturing a semiconductor memory device, the method comprising: forming a first layer on a semiconductor layer by immersing the semiconductor layer in a first solution containing a first precursor described by molecular formula (1); forming a second layer on the first layer by immersing the first layer in a second solution containing a second precursor described by molecular formula (2); forming an organic molecular layer containing oxidation-reduction molecules on a surface of the second layer; and forming a control gate electrode on the organic molecular layer: wherein X, Y are independently selected from among silyl ether, phosphoryl ether, alkoxy, carbonyl, and ether, n is an integer greater than 0, R 1 to R 4 are independently selected from hydrogen, oxygen, silicon, hydrocarbon, halogen, halogenated silane, alkoxy silane, and silyl ether, and m is an integer greater than 0. 20 . The method according to claim 19 , further comprising forming an inorganic insulating layer on the semiconductor layer before forming the first layer.

Assignees

Inventors

Classifications

  • carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC · CPC title

  • Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating · CPC title

  • H10D64/037Primary

    comprising charge-trapping insulators · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

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What does patent US2016284868A1 cover?
A semiconductor memory device in an embodiment includes a semiconductor layer, a control gate electrode, an organic molecular layer provided between the semiconductor layer and the control gate electrode, and a first insulating layer provided between the organic molecular layer and the semiconductor layer, the first insulating layer having a first layer containing alkyl chains and a second laye…
Who is the assignee on this patent?
Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification H10P14/6342. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Sep 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).