Semiconductor device and inverter circuit

Patent metadata

Field	Value
Publication number	US-2016284833-A1
Application number	US-201615055795-A
Country	US
Kind code	A1
Filing date	Feb 29, 2016
Priority date	Mar 24, 2015
Publication date	Sep 29, 2016
Grant date	—

Abstract

A semiconductor device according to embodiments includes a p-type SiC layer having a first plane, a gate electrode, and a gate insulating layer provided between the first plane of the SiC layer and the gate electrode. The gate insulating layer includes a first layer, a second layer, and a first region. The second layer has a higher oxygen density than the first layer. The first region is provided between the first layer and the second layer and includes a first element, the first element being at least one element in the group of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), and Bi (bismuth).

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a p-type SiC layer having a first plane; a gate electrode; and a gate insulating layer provided between the first plane and the gate electrode, the gate insulating layer including; a first layer, a second layer having a higher oxygen density than the first layer, and a first region provided between the first layer and the second layer, the first region including a first element, the first element being at least one element in the group of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), and Bi (bismuth).

2 . The semiconductor device according to claim 1 , wherein the first region has a first concentration peak of the first element.

3 . The semiconductor device according to claim 2 , wherein a full width at half maximum of the first concentration peak is equal to or less than 1 nm.

4 . The semiconductor device according to claim 2 , wherein concentration of the first concentration peak is 4×10 19 cm −3 or more and 6.4×10 22 cm −3 or less.

5 . The semiconductor device according to claim 1 , wherein the second layer is provided between the first layer and the gate electrode.

6 . The semiconductor device according to claim 1 , wherein the second layer contacts with the gate electrode.

7 . The semiconductor device according to claim 1 , wherein the first layer and the second layer are one of materials in the group of silicone oxide, aluminum oxide, hafnium oxide, zirconium oxide, hafnium aluminum oxide, zirconium aluminum oxide, hafnium silicate, and zirconium silicate.

8 . The semiconductor device according to claim 1 , further comprising a second region provided between the SiC layer and the gate insulating layer, the second region including a second element, the second element being at least one second element in the group of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), and Bi (bismuth).

9 . The semiconductor device according to claim 8 , wherein the second region has a second concentration peak of the second element.

10 . The semiconductor device according to claim 9 , wherein a full width at half maximum of the second concentration peak is equal to or less than 1 nm.

11 . The semiconductor device according to claim 9 , wherein concentration of the second concentration peak is 4×10 19 cm −3 or more and 6.4×10 22 cm −3 or less.

12 . The semiconductor device according to claim 8 , wherein the first element and the second element are the same.

13 . The semiconductor device according to claim 8 , wherein the first plane is a plane inclined at 0° or more and 8° or less with respect to a (0001) face, and the second element is P (phosphorus) or As (arsenic).

14 . The semiconductor device according to claim 8 , wherein the first plane is a plane inclined at 0° or more and 8° or less with respect to a (000-1) face, or the first plane is a plane inclined at 0° or more and 8° or less with respect to a <0001> direction, and the second element is N (nitrogen).

15 . A semiconductor device, comprising:
a p-type SiC layer; a gate electrode; and a gate insulating layer provided between the SiC layer and the gate electrode, the gate insulating layer including C (carbon) and at least one element in the group of Ge (germanium), B (boron), Al (aluminum), Ga (gallium), In (indium), Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), Ba (barium), Sc (scandium), Y (yttrium), La (lantern), and lanthanoid (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu).

16 . The semiconductor device according to claim 15 , wherein a maximum concentration of the at least one element in the gate insulating layer is equal to or greater than 1×10 18 cm −3 .

17 . The semiconductor device according to claim 15 , wherein a maximum concentration of C (carbon) in the gate insulating layer is equal to or greater than 1×10 18 cm −1 .

18 . The semiconductor device according to claim 15 , wherein a maximum concentration of the at least one element in the gate insulating layer is 80% more and the 120% or less of a maximum concentration of C (carbon) in the gate insulating layer.

19 . The semiconductor device according to claim 15 , wherein a concentration of the at least one element at a first position in the gate insulating layer is 80% more and 120% or less of a concentration of C (carbon) at the first position.

20 . An inverter circuit comprising the semiconductor device according to claim 1 .

Assignees

• Toshiba Kk

Inventors

• Shimizu Tatsuo
• Lljima Ryosuke

Classifications

• H10D64/01366

  the semiconductor being silicon carbide · CPC title

• H10D30/66 Primary

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/685

  being perpendicular to the channel plane · CPC title