Method of formation of a substrate of the soi, in particular the fdsoi, type adapted to transistors having gate dielectrics of different thicknesses, corresponding substrate and integrated circuit

Patent metadata

Field	Value
Publication number	US-2016284807-A1
Application number	US-201514930324-A
Country	US
Kind code	A1
Filing date	Nov 2, 2015
Priority date	Mar 27, 2015
Publication date	Sep 29, 2016
Grant date	—

Abstract

A substrate of the silicon-on-insulator type is formed from an initial substrate of the silicon-on-insulator type having a semiconductor film on top of a buried insulating layer itself situated on top of a carrier substrate. A localized modification of a thickness of the semiconductor film is made so as to form a semiconductor film having different thicknesses in different regions.

First claim

1 . A method for the formation of a substrate of the silicon-on-insulator type, comprising:
processing an initial substrate of the silicon-on-insulator type having a semiconductor film on top of a buried insulating layer itself situated on top of a carrier substrate to produce at least one localized modification of a thickness of the semiconductor film so as to form semiconductor film regions having different thicknesses in different substrate regions.

2 . The method according to claim 1 , wherein processing comprises:
masking the semiconductor film in at least a first substrate region with a mask; forming in at least a second substrate region at least one protection layer that consumes a part of the semiconductor film in the second substrate region; and removing the mask and the protection layer.

3 . The method according to claim 2 , further comprising:
forming a first transistor with a gate dielectric of a first thickness on the semiconductor film in the first substrate region; and forming a second transistor with a gate dielectric of a second thickness on the semiconductor film in the second substrate region.

4 . The method of claim 3 , wherein the gate dielectric of the first thickness is thicker than the gate dielectric of the second thickness.

5 . The method according to claim 1 , wherein producing comprises:
forming a protection layer on the semiconductor film; removing the protection layer over a first substrate region while leaving the protection layer in place over a second substrate region; growing by epitaxy of the silicon type on the semiconductor film in the first substrate region to increase a thickness of the semiconductor film in the first substrate region; and removing the protection layer from over the second substrate region.

6 . The method according to claim 5 , further comprising:
forming a first transistor with a gate dielectric of a first thickness on the semiconductor film in the first substrate region; and forming a second transistor with a gate dielectric of a second thickness on the semiconductor film in the second substrate region.

7 . The method of claim 6 , wherein the gate dielectric of the first thickness is thicker than the gate dielectric of the second thickness.

8 . The method according to claim 1 , wherein the substrate is of a fully-depleted silicon-on-insulator type.

9 . A substrate of a silicon-on-insulator type, comprising:
a semiconductor film having different thicknesses in different substrate regions and resting on a same buried insulating layer itself situated on top of a same carrier substrate.

10 . The substrate according to claim 9 , wherein the substrate is of a fully-depleted silicon-on-insulator type.

11 . The substrate according to claim 10 , further comprising an insulation structure between the different substrate regions.

12 . An integrated circuit, comprising:
a substrate of the silicon-on-insulator type comprising a semiconductor film having different thicknesses in different substrate regions and resting on a same buried insulating layer itself situated on top of a same carrier substrate; a first transistor with a first gate dielectric having a first thickness in a first substrate region where the semiconductor film has a first thickness; and a second transistor with a second gate dielectric having a second thickness in a second substrate region where the semiconductor film has a second thickness, wherein said second thickness of the second gate dielectric is thicker than the first thickness of the first gate dielectric, and wherein said second thickness of the semiconductor film is thicker than the first thickness of the semiconductor film.

13 . The integrated circuit according to claim 12 , wherein the substrate is of a fully-depleted silicon-on-insulator type.

14 . The integrated circuit according to claim 12 , further comprising an insulation structure between the first and second substrate regions.

Assignees

• St Microelectronics Crolles 2 Sas
• St Microelectronics Sa

Inventors

• Petit David
• Monsieur Frederic
• Federspiel Xavier
• Bidal Gregory

Classifications

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10W10/011 Primary

  of isolation regions comprising dielectric materials · CPC title

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title