Semiconductor device, inverter circuit, and vehicle

US2016284804A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016284804-A1
Application numberUS-201615055848-A
CountryUS
Kind codeA1
Filing dateFeb 29, 2016
Priority dateMar 24, 2015
Publication dateSep 29, 2016
Grant date

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A semiconductor device according to embodiments described herein includes a p-type SiC layer, a gate electrode, and a gate insulating layer between the SiC layer and the gate electrode. The gate insulating layer includes a first layer, a second layer, a first region, and a second region. The second layer is between the first layer and the gate electrode and has a higher oxygen density than the first layer. The first region is provided across the first layer and the second layer, includes a first element from F, D, and H, and has a first concentration peak of the first element. The second region is provided in the first layer, includes a second element from Ge, B, Al, Ga, In, Be, Mg, Ca, Sr, Ba, Sc, Y, La, and lanthanoid, and has a second concentration peak of the second element and a third concentration peak of C.

First claim

Opening claim text (preview).

What is claimed is: 1 . A semiconductor device, comprising: a p-type SiC layer; a gate electrode; and a gate insulating layer provided between the SiC layer and the gate electrode, the gate insulating layer including; a first layer, a second layer provided between the first layer and the gate electrode, the second layer having a higher oxygen density than the first layer, a first region provided across the first layer and the second layer, the first region including a first element which is at least one element in the group of F (fluorine), D (deuterium), and H (hydrogen) and the first region having a first concentration peak of the first element, and a second region provided in the first layer, the second region including a second element which is at least one element in the group of Ge (germanium), B (boron), Al (aluminum), Ga (gallium), In (indium), Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), Ba (barium), Sc (scandium), Y (yttrium), La (lantern), and lanthanoid (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu) and the second region having a second concentration peak of the second element and a third concentration peak of C (carbon), a distance between the second concentration peak and the third concentration peak being shorter than a distance between the first concentration peak and the third concentration peak. 2 . The semiconductor device according to claim 1 , wherein a distance between the second concentration peak and the first concentration peak is equal to or less than 4 nm, and the distance between the first concentration peak and the third concentration peak is equal to or less than 4 nm. 3 . The semiconductor device according to claim 1 , wherein full widths at half maximum of the first concentration peak and the second concentration peak are equal to or less than 1 nm. 4 . The semiconductor device according to claim 1 , wherein a full width at half maximum of the third concentration peak is equal to or less than 1 nm. 5 . The semiconductor device according to claim 1 , wherein the first layer is a silicone oxide film. 6 . The semiconductor device according to claim 1 , wherein the second layer is a hafnium oxide film or a zirconium oxide film. 7 . A semiconductor device, comprising: a p-type SiC layer; a gate electrode; and a gate insulating layer provided between the SiC layer and the gate electrode, the gate insulating layer including; a first layer, a second layer provided between the first layer and the gate electrode, the second layer having a higher oxygen density than the first layer, a first region provided in the second layer, the first region including a first element which is at least one element in the group of Ta (tantalum), Nb (niobium), and V (vanadium) and the first region having a first concentration peak of the first element; and a second region provided in the first layer, the second region including a second element which is at least one element in the group of Ge (germanium), B (boron), Al (aluminum), Ga (gallium), In (indium), Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), Ba (barium), La (lantern), and lanthanoid (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu) and the second region having a second concentration peak of the second element and a third concentration peak of C (carbon), a distance between the second concentration peak and the third concentration peak being shorter than a distance between the first concentration peak and the third concentration peak. 8 . The semiconductor device according to claim 7 , wherein a distance between the second concentration peak and the first concentration peak is equal to or less than 4 nm, and the distance between the first concentration peak and the third concentration peak is equal to or less than 4 nm. 9 . The semiconductor device according to claim 7 , wherein full widths at half maximum of the first concentration peak and the second concentration peak are equal to or less than 1 nm. 10 . The semiconductor device according to claim 7 , wherein a full width at half maximum of the third concentration peak is equal to or less than 1 nm. 11 . The semiconductor device according to claim 7 , wherein the first layer is a silicone oxide film. 12 . The semiconductor device according to claim 7 , wherein the second layer is a hafnium oxide film or a zirconium oxide film. 13 . A semiconductor device, comprising: a p-type SiC layer; a gate electrode; and a gate insulating layer provided between the SiC layer and the gate electrode, the gate insulating layer including; a first layer, a second layer provided between the first layer and the gate electrode, the second layer having a lower oxygen density than the first layer, a first region provided across the first layer and the second layer, the first region including a first element which is at least one element in the group of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), and Bi (bismuth) and the first region having a first concentration peak of the first element, and a second region provided in the second layer, the second region including a second element which is at least one element in the group of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), and Bi (bismuth) and the second region having a second concentration peak of the second element and a third concentration peak of C (carbon), a distance between the second concentration peak and the third concentration peak being shorter than a distance between the first concentration peak and the third concentration peak. 14 . The semiconductor device according to claim 13 , wherein a distance between the second concentration peak and the first concentration peak is equal to or less than 4 nm, and the distance between the first concentration peak and the third concentration peak is equal to or less than 4 nm. 15 . The semiconductor device according to claim 13 , wherein full widths at half maximum of the first concentration peak and the second concentration peak are equal to or less than 1 nm. 16 . The semiconductor device according to claim 13 , wherein a full width at half maximum of the third concentration peak is equal to or less than 1 nm. 17 . The semiconductor device according to claim 13 , wherein the second layer is a silicone oxide film. 18 . The semiconductor device according to claim 13 , wherein the first layer is a hafnium oxide film or a zirconium oxide film. 19 . An inverter circuit, comprising the semiconductor device according to claim 1 . 20 . A vehicle comprising the semiconductor device according to claim 1 .

Assignees

Inventors

Classifications

  • Vertical DMOS [VDMOS] FETs · CPC title

  • the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

  • comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

  • being perpendicular to the channel plane · CPC title

  • Silicon carbide · CPC title

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What does patent US2016284804A1 cover?
A semiconductor device according to embodiments described herein includes a p-type SiC layer, a gate electrode, and a gate insulating layer between the SiC layer and the gate electrode. The gate insulating layer includes a first layer, a second layer, a first region, and a second region. The second layer is between the first layer and the gate electrode and has a higher oxygen density than the …
Who is the assignee on this patent?
Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification H10D62/8325. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Sep 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).