Memory controller that controls a plurality of memory devices, and printing apparatus including memory controller

Patent metadata

Field	Value
Publication number	US-2016284385-A1
Application number	US-201414904438-A
Country	US
Kind code	A1
Filing date	Sep 12, 2014
Priority date	Sep 13, 2013
Publication date	Sep 29, 2016
Grant date	—

Abstract

A memory controller that enables reduction of calibration time. A memory controller controls a plurality of memory devices. A result of calibration on a memory configuration to be set at the start of a multifunction peripheral and results of calibration on other memory configurations than the memory configuration to be set at the startup of the multifunction peripheral are stored. Settings of the memory controller and settings of the memory devices are made using a result of calibration on the memory configuration adapted to the standby mode or the normal operation mode, which is selected from the stored calibration results.

First claim

1 - 8 . (canceled)

9 . A memory controller that controls first memory device and a second memory device, comprising:
a power supply control unit configured to control power supply to the first memory device and the second memory device; a storage unit configured to store a first setting value for adjusting writing timing in a first power state of writing of data in the first memory device, or reading timing in the first power state of data from the first memory device in the first power state, the first power state indicating a state where the power is supplied to the first memory device and the second memory device, and a second setting value for adjusting a writing timing in a second power state of data in the first memory device, or a reading timing in the second power state of data from the first memory device, the second power state indicating a state where the power is supplied to the first memory device while the power supply to the second memory is stopped; and a control unit configured to control, in the first power state, the writing timing of the data in the first memory device or the reading timing of the data from the first memory device based on the first setting value stored in the storage unit, and control, in the second power state, the writing timing of the data in the first memory device, or the reading timing of the data from the first memory device, based on the second setting value stored in the storage unit.

10 . The memory controller according to claim 9 , further comprising a memory device information acquisition unit configured to acquire information on the plurality of memory devices, and
wherein said power supply control unit controls power supply to the first memory device and the second memory device based on the memory device information acquired by said memory device information acquisition unit.

11 . The memory controller according to claim 10 , wherein the memory device information includes a memory capacity of the first memory device and a memory capacity of the second memory device.

12 . The memory controller according to claim 10 , wherein the memory device information includes types of the plurality of memory devices.

13 . The memory controller according to claim 9 , wherein the first memory device and the second memory device are disposed on a single bus.

Assignees

• Canon Kk

Inventors

• Nomura Yoshihisa

Classifications

• H04N2201/0094

  Multifunctional device, i.e. a device capable of all of reading, reproducing, copying, facsimile transception, file transception · CPC title

• H04N1/21 Primary

  Intermediate information storage (H04N1/387, H04N1/41 take precedence {; for control between transmitter and receiver or between image input and image output device H04N1/32358; indexing, editing G11B27/00}) · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F12/0646

  Configuration or reconfiguration · CPC title

• G06F1/3284

  Power saving in printer · CPC title