Subscriber station for a bus system and method for reducing line-conducted emissions in a bus system

Patent metadata

Field	Value
Publication number	US-2016283435-A1
Application number	US-201415033557-A
Country	US
Kind code	A1
Filing date	Oct 20, 2014
Priority date	Nov 8, 2013
Publication date	Sep 29, 2016
Grant date	—

Abstract

A subscriber station for a bus system and a method for reducing line-conducted emissions in a bus system are provided. The subscriber station includes a first delay element for delaying a signal of a bus of the bus system and a second delay element for delaying a signal of a bus of the bus system, the delay time of the first and second delay element being capable of being digitally set as a function of the bus state or independently for rising and falling signal edges at the bus of the bus system in order to carry out a signal symmetrization during the rising and falling signal edge at the bus.

First claim

1 - 10 . (canceled)

11 . A subscriber station for a bus system, comprising:
a first delay element for delaying a signal of a bus of the bus system; and a second delay element for delaying a signal of a bus of the bus system; wherein delay times of the first and second delay elements can be digitally set one of: i) as a function of a bus state, or ii) independently for rising and falling signal edges at the bus of the bus system, to carry out a signal symmetrization during the rising and falling signal edge at the bus.

12 . The subscriber station as recited in claim 11 , further comprising:
a transmit device for transmitting signals to the bus; wherein the first and second delay elements are situated in one of: i) a CAN_L signal path, or ii) in the CAN_H signal path of the transmit device.

13 . The subscriber station as recited in claim 11 , wherein the first and second delay elements are fashioned such that the delay times of the first and second delay elements are definitely smaller to definitely larger than a comparable delay time of a complementary path.

14 . The subscriber station as recited in claim 11 , further comprising:
a summation block for a summation of voltage at the bus; a capacitor for filtering the sum voltage output by the summation block; and an analog-digital converter for evaluating the sum voltage filtered by the capacitor to carry out a signal symmetrization during the rising and falling signal edge at the bus.

15 . The subscriber station as recited in claim 14 , wherein the subscriber station is fashioned to evaluate voltage peaks in the sum voltage with regard to at least one of i) their amplitude level, and ii) their temporal width.

16 . The subscriber station as recited in claim 14 , further comprising:
a first accumulation register for counting voltage peaks in the sum voltage at the recessive-dominant transition of a bus signal and a second accumulation register for counting voltage peaks in the sum voltage at a dominant-recessive transition of the bus signal; wherein the subscriber station is configured so that:
for the recessive-dominant transition, given a positive voltage peak in the sum voltage, the first accumulation register is incremented, and a delay of the first delay element is reduced; and
for the dominant-recessive transition, given a positive voltage peak in the sum voltage, the second accumulation register is incremented, and a delay of the second delay element is reduced.

17 . A bus system, comprising:
a bus; and at least two subscriber stations connected to one another via the bus in such a way that the subscriber stations are capable of communicating with each other, at least one of the at least two subscriber stations including a first delay element for delaying a signal of a bus of the bus system, and a second delay element for delaying a signal of a bus of the bus system, wherein delay times of the first and second delay elements can be digitally set one of: i) as a function of a bus state, or ii) independently for rising and falling signal edges at the bus of the bus system, to carry out a signal symmetrization during the rising and falling signal edge at the bus.

18 . A method for reducing line-conducted emissions in a bus system, a subscriber station of the bus system including a first delay element for delaying a signal of a bus of the bus system, and a second delay element for delaying a signal of a bus of the bus system, the method comprising:
digitally setting delay times of the first and second delay elements one of: i) as a function of the bus state, or ii) independently for rising and falling signal edges at the bus of the bus system, to carry out a signal symmetrization during the rising and falling signal edge at the bus.

19 . The method as recited in claim 18 , wherein the delay elements are fashioned such that the delay times of the first and second delay elements are definitely smaller to definitely larger than a comparable delay time of a complementary path.

20 . The method as recited in claim 18 , further comprising:
summing, by a summation block of the subscriber station, a voltage at the bus; filtering, by a capacitor of the subscriber station, the sum voltage output by the summation block; and evaluating, by an analog-digital converter of the subscriber station, the sum voltage filtered by the capacitor to carry out a signal symmetrization during a rising and falling signal edge at the bus.

21 . The method as recited in claim 20 , further comprising:
evaluating voltage peaks in the sum voltage with regard to at least one of their amplitude level and their temporal width.

22 . The method as recited in claim 21 , further comprising:
counting, by a first accumulation register, voltage peaks in the sum voltage during the recessive-dominant transition of a bus signal; and counting, by a second accumulation register, voltage peaks in the sum voltage during the dominant-recessive transition of the bus signal; wherein, for the recessive-dominant transition, given a positive voltage peak in the sum voltage, the first accumulation register is incremented, and a delay of the first delay element is reduced; and wherein, for the dominant-recessive transition, given a positive voltage peak in the sum voltage, the second accumulation register is incremented, and a delay of the second delay element is reduced.

Assignees

• Bosch Gmbh Robert

Inventors

• Walker Steffen
• Pannwitz Axel
• Hehemann Ingo

Classifications

• H04L27/2614

  Peak power aspects · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• H04L25/0274 Primary

  Arrangements for ensuring balanced coupling · CPC title

• H04L2012/40215

  Controller Area Network CAN · CPC title

• G06F13/4291 Primary

  using a clocked protocol · CPC title