Input/output control device, information processing apparatus, and control method of the input/output control device

Patent metadata

Field	Value
Publication number	US-2016283305-A1
Application number	US-201615002460-A
Country	US
Kind code	A1
Filing date	Jan 21, 2016
Priority date	Mar 27, 2015
Publication date	Sep 29, 2016
Grant date	—

Abstract

A PCIe processing unit is connected to a PCI device. A BDF information extracting unit specifies, in response to an occurrence notification of an error, a PCI device in which the error has occurred. An AER address searching unit detects the AER address that is the storage location of error information related to the error held by the PCI device specified by the BDF information extracting unit. An error information acquiring unit collects error information from the AER address that is stored in the PCI device and that is detected by the AER address searching unit. An interrupt determination unit transmits the error information collected by the error information acquiring unit to a core.

First claim

What is claimed is:

1 . An input/output control device connected to a processing unit, the input/output control device comprising:
a specifying unit that specifies, in response to an occurrence notification of an error, a processing unit in which the error has occurred; a detecting unit that detects a storage location of error information related to the error held by the processing unit specified by the specifying unit; a collecting unit that collects the error information from the storage location that is stored in the processing unit and that is detected by the detecting unit; and a transmission unit that transmits the error information collected by the collecting unit to an arithmetic processing device.

2 . The input/output control device according to claim 1 , wherein, when the specifying unit receives an occurrence notification of another error before the transmission unit transmits the error information, the transmission unit waits until the error information related to the other error is collected by the collecting unit and collectively transmits all of the pieces of the collected error information to the arithmetic processing device.

3 . The input/output control device according to claim 2 , wherein, when the number of pieces of the error information collected by the collecting unit reaches a threshold in a standby time period of the transmission of the error information, the transmission unit transmits the error information collected by that time to the arithmetic processing device.

4 . The input/output control device according to claim 1 , wherein
the processing unit includes a storing unit that stores therein the error information, and the detecting unit detects the address of the storage location of the error information stored in the storing unit.

5 . The input/output control device according to claim 1 , wherein
the storing unit stores therein a plurality of pieces of information including the error information and each of the pieces of the information include location information that indicates the location of subsequent information, and the detecting unit detects, on the basis of the location information, the storage location of the error information by sequentially detecting the subsequent information from predetermined information that is included in the plurality of pieces of the information stored in the storing unit.

6 . The input/output control device according to claim 1 , wherein the detecting unit previously stores, at the time of start up, information on the storage location of the error information in the storing unit in the processing unit.

7 . The input/output control device according to claim 1 , further comprising a determination unit that determines, in response to the occurrence notification of the error, the level of the error that has occurred, that causes, when the error is a serious error, the transmission unit to send the occurrence notification of the error to the arithmetic processing device, and that transmits, when the error is not the serious error, the occurrence notification of the error to the detecting unit.

8 . An information processing apparatus comprising:
an arithmetic processing unit; a processing unit that performs a process in response to an instruction received from the arithmetic processing unit; a switch that relays communication between the arithmetic processing unit and the processing unit; a specifying unit that specifies, in response to an occurrence notification of an error, the processing unit in which the error has occurred; a detecting unit that detects the storage location of error information related to the error held by the processing unit specified by the specifying unit; a collecting unit that collects the error information from the storage location that is stored in the processing unit and that is detected by the detecting unit; and a transmission unit that transmits the error information collected by the collecting unit to the arithmetic processing unit.

9 . A control method of an input-output device connected to a processing unit, the control method comprising:
specifying, performed by a specifying unit included in the input-output device, in response to an occurrence notification of an error, a processing unit in which the error has occurred; detecting, performed by a detecting unit included in the input-output device, the storage location of error information related to the error held by the processing unit specified by the specifying unit; collecting, performed by a collecting unit included in the input-output device, the error information from the detected storage location stored in the processing unit; and sending, performed by a transmission unit included in the input-output device, the collected error information to an arithmetic processing unit.

Assignees

• Fujitsu Ltd

Inventors

• Kugata Kouji

Classifications

• G06F13/36 Primary

  for access to common bus or bus system · CPC title

• G06F11/0751

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F11/0745

  in an input/output transactions management context (input/output processing in general G06F13/00) · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title