Apparatuses and methods to selectively execute a commit instruction

Patent metadata

Field	Value
Publication number	US-2016283247-A1
Application number	US-201514668605-A
Country	US
Kind code	A1
Filing date	Mar 25, 2015
Priority date	Mar 25, 2015
Publication date	Sep 29, 2016
Grant date	—

Abstract

Methods and apparatuses relating to selectively executing a commit instruction. In one embodiment, a data storage device stores code that when executed by a hardware processor causes the hardware processor to perform the following: translating an instruction into a translated instruction to be executed by the hardware processor, marking a commit instruction one of for execution and for optional execution by the hardware processor, and including a hint for a commit instruction marked for optional execution; and a hardware commit unit to determine if the commit instruction marked for optional execution is to be executed based on the hint.

First claim

What is claimed is:

1 . An apparatus comprising:
a hardware binary translator to:
translate an instruction into a translated instruction to be executed by a hardware processor;
mark a commit instruction one of for execution and for optional execution by the hardware processor;
and

include a hint for a commit instruction marked for optional execution; and
a hardware commit unit to determine if the commit instruction marked for optional execution is to be executed based on the hint.

2 . The apparatus of claim 1 , wherein the translated instruction follows the commit instruction in program order.

3 . The apparatus of claim 1 , wherein the hardware commit unit is to cause a next commit instruction to be executed based on the hint for the commit instruction.

4 . The apparatus of claim 1 , wherein the hardware binary translator is to include the hint as a field of the commit instruction marked for optional execution.

5 . The apparatus of claim 1 , wherein the hardware commit unit is to cause a block of instructions executed out of order before a rollback action to be executed in order after the rollback action.

6 . The apparatus of claim 5 , wherein the hardware commit unit is to cause all commit instructions marked for optional execution of the block of instructions to be executed independently of their hint after the rollback action.

7 . An apparatus comprising:
a data storage device that stores code that when executed by a hardware processor causes the hardware processor to perform the following:
translating an instruction into a translated instruction to be executed by the hardware processor;
marking a commit instruction one of for execution and for optional execution by the hardware processor; and
including a hint for a commit instruction marked for optional execution; and
a hardware commit unit to determine if the commit instruction marked for optional execution is to be executed based on the hint.

8 . The apparatus of claim 7 , wherein the translated instruction follows the commit instruction in program order.

9 . The apparatus of claim 7 , wherein the data storage device further stores code that when executed by the hardware processor causes the hardware processor to perform the following:
causing a next commit instruction to be executed based on the hint for the commit instruction.

10 . The apparatus of claim 7 , wherein the data storage device further stores code that when executed by the hardware processor causes the hardware processor to perform the following:
wherein the including comprises including the hint as a field of the commit instruction marked for optional execution.

11 . The apparatus of claim 7 , wherein the data storage device further stores code that when executed by the hardware processor causes the hardware processor to perform the following:
causing a block of instructions executed out of order before a rollback action to be executed in order after the rollback action.

12 . The apparatus of claim 11 , wherein the data storage device further stores code that when executed by the hardware processor causes the hardware processor to perform the following:
causing all commit instructions marked for optional execution of the block of instructions to be executed independently of their hint after the rollback action.

13 . A method comprising:
translating an instruction into a translated instruction to be executed by a hardware processor; marking a commit instruction one of for execution and for optional execution by the hardware processor; including a hint for a commit instruction marked for optional execution; and determining if the commit instruction marked for optional execution is to be executed based on the hint.

14 . The method of claim 13 , wherein the translated instruction follows the commit instruction in program order.

15 . The method of claim 13 , further comprising causing a next commit instruction to be executed based on the hint for the commit instruction.

16 . The method of claim 13 , wherein the including comprises including the hint as a field of the commit instruction marked for optional execution.

17 . The method of claim 13 , further comprising causing a block of instructions executed out of order before a rollback action to be executed in order after the rollback action.

18 . The method of claim 17 , further comprising causing all commit instructions marked for optional execution of the block of instructions to be executed independently of their hint after the rollback action.

19 . An apparatus comprising:
a hardware processor; and a data storage device that stores code that when executed by the hardware processor causes the hardware processor to perform the following:
translating an instruction into a translated instruction to be executed by the hardware processor;
marking a commit instruction one of for execution and for optional execution by the hardware processor;
including a hint for a commit instruction marked for optional execution; and
determining if the commit instruction marked for optional execution is to be executed based on the hint.

20 . The apparatus of claim 19 , wherein the translated instruction follows the commit instruction in program order.

21 . The apparatus of claim 19 , wherein the data storage device further stores code that when executed by the hardware processor causes the hardware processor to perform the following:
further comprising causing a next commit instruction to be executed based on the hint for the commit instruction.

22 . The apparatus of claim 19 , wherein the data storage device further stores code that when executed by the hardware processor causes the hardware processor to perform the following:
wherein the including comprises including the hint as a field of the commit instruction marked for optional execution.

23 . The apparatus of claim 19 , wherein the data storage device further stores code that when executed by the hardware processor causes the hardware processor to perform the following:
further comprising causing a block of instructions executed out of order before a rollback action to be executed in order after the rollback action.

24 . The apparatus of claim 23 , wherein the data storage device further stores code that when executed by the hardware processor causes the hardware processor to perform the following:
further comprising causing all commit instructions marked for optional execution of the block of instructions to be executed independently of their hint after the rollback action.

Assignees

• Intel Corp

Inventors

• Venkatasubramanian Girish
• Schuchman Ethan
• Keppel David
• Winkel Sebastian
• Mackintosh David N
• Topp Jaroslaw

Classifications

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/3842 Primary

  Speculative instruction execution · CPC title

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/30087 Primary

  Synchronisation or serialisation instructions · CPC title

• G06F9/3863

  using multiple copies of the architectural state, e.g. shadow registers · CPC title