Parallel data processing apparatus

Patent metadata

Field	Value
Publication number	US-2016283241-A1
Application number	US-201615073573-A
Country	US
Kind code	A1
Filing date	Mar 17, 2016
Priority date	Apr 9, 1999
Publication date	Sep 29, 2016
Grant date	—

Abstract

A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus includes an instruction controller operable to receive instructions from a plurality of instructions streams, and to transfer instructions from those instructions streams to the processing elements in the array, such that the data processing apparatus is operable to process a plurality of processing threads substantially in parallel with one another. A data transfer controller is provided which is operable to control transfer of data between the internal memory units associated with the processing elements, and memory external to the array.

First claim

What is claimed is:

1 . An array controller for controlling operation of a single instruction multiple data (SIMD) array of processing elements, comprising:
memory for maintaining results corresponding to instruction execution while executing load/store instructions and processing element instructions, the load/store instructions encoded with information indicating which registers of a register file of the respective processing elements are accessed by the respective load/store instructions; an instruction table to provide a first plurality of register indicators when addressed by a plurality of bits of a first processing element instruction to be executed; an instruction launcher, the instruction launcher to receive the first plurality of register indicators and to lock first respective registers of the register file that correspond to the first plurality of register indicators when the first processing element instruction is launched.

2 . The array controller of claim 1 , wherein, when a second processing element instruction is launched while the first processing element instruction is executing, the instruction launcher is to also receive a second plurality of register indicators and is to also lock second respective registers of the register file that correspond to the second plurality of register indicators.

3 . The array controller of claim 2 , wherein the execution of the second processing element instruction is stalled based on the second processing element instruction accessing at least one of the first respective registers of the register file that correspond to the first plurality of register indicators.

4 . The array controller of claim 2 , wherein the memory comprises a register file.

5 . The array controller of claim 2 , wherein the second processing element instruction is launched when the second processing element accesses at least one of the first respective registers of the register file that correspond to the first plurality of register indicators.

6 . The array controller of claim 1 , wherein when a load/store instruction encoded with information indicating which registers of the register file are accessed by the load/store instruction is launched while the first processing element instruction is executing, the instruction launcher is to also receive a second plurality of register indicators based on the information indicating which registers of the register file are accessed by the load/store instruction and is to also lock second respective registers of the register file that correspond to the second plurality of register indicators.

7 . The array controller of claim 6 , wherein the execution of the load/store instruction is stalled based on the load/store instruction accessing at least one of the first respective registers of the register file that correspond to the first plurality of register indicators.

8 . A system, comprising:
a plurality of single instruction multiple data (SIMD) array of processing elements; a register file to maintain results corresponding to instruction execution by the plurality of SIMD array of processing elements while the system executes load/store instructions and processing element instructions, the load/store instructions encoded with information indicating which registers of the register file are accessed by the respective load/store instructions, an instruction table to provide a first plurality of register indicators when addressed by a plurality of bits of a first processing element instruction to be executed; an instruction launcher, the instruction launcher to receive the first plurality of register indicators and to lock first respective registers of the register file that correspond to the first plurality of register indicators when the first processing element instruction is launched.

9 . The system of claim 8 , wherein, when a second processing element instruction is launched while the first processing element instruction is executing, the instruction launcher is to also receive a second plurality of register indicators and the instruction launcher is to also lock second respective registers of the register file that correspond to the second plurality of register indicators.

10 . The system of claim 9 , wherein the execution of the second processing element instruction is stalled based on the second processing element instruction accessing at least one of the first respective registers of the register file that correspond to the first plurality of register indicators.

11 . The system of claim 9 , wherein an execution of the second processing element instruction is stalled based on an execution of the first processing element instruction being incomplete.

12 . The system of claim 9 , wherein the second processing element instruction is launched when the second processing element accesses at least one of the first respective registers of the register file that correspond to the first plurality of register indicators.

13 . The system of claim 8 , wherein when a load/store instruction encoded with information indicating which registers of the register file are accessed by the load/store instruction is launched while the first processing element instruction is executing, the instruction launcher is to also receive a second plurality of register indicators based on the information indicating which registers of the register file are accessed by the load/store instruction and is to also lock second respective registers of the register file that correspond to the second plurality of register indicators.

14 . The system of claim 13 , wherein the execution of the load/store instruction is stalled based on the load/store instruction accessing at least one of the first respective registers of the register file that correspond to the first plurality of register indicators.

15 . An integrated circuit, comprising:
a single instruction multiple data (SIMD) array of processing elements, the processing elements including a register file; a scoreboard unit to store information regarding use of registers of the register file during execution of load/store instructions and processing element instructions, the load/store instructions encoded with information indicating which registers of the register file are accessed by a respective load/store instruction; an instruction table to provide a first plurality of register indicators when addressed by a plurality of bits of a first processing element instruction to be executed; an instruction launcher, the instruction launcher to receive the first plurality of register indicators and to lock first respective registers of the register file that correspond to the first plurality of register indicators when the first processing element instruction is launched.

16 . The integrated circuit of claim 15 , wherein when a load/store instruction encoded with information indicating which registers of the register file are accessed by the load/store instruction is launched while the first processing element instruction is executing, the instruction launcher is to also receive a second plurality of register indicators based on the information indicating which registers of the register file are accessed by the load/store instruction and is to also lock second respective registers of the register file that correspond to the second plurality of register indicators.

17 . The integrated circuit of claim 16 , wherein the execution of the load/store instruction is stalled based on the load/store instruction accessing at least one of the first respective registers of the register fil

Assignees

• Rambus Inc

Inventors

• Stuttard Dave
• Williams Dave
• O'Dea Eamon
• Faulds Gordon
• Rhoades John
• Cameron Ken
• Atkin Phil
• Winser Paul
• David Russell
• Mcconnell Ray
• Day Tim
• Greer Trey

Classifications

• G06F15/8007

  single instruction multiple data [SIMD] multiprocessors · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/30094

  Condition code generation, e.g. Carry, Zero flag · CPC title

• G06F9/3009

  Thread control instructions · CPC title

• G06F9/30087

  Synchronisation or serialisation instructions · CPC title