Configurable multi-lane scrambler for flexible protocol support

Patent metadata

Field	Value
Publication number	US-2016277221-A1
Application number	US-201615167785-A
Country	US
Kind code	A1
Filing date	May 27, 2016
Priority date	Jul 30, 2010
Publication date	Sep 22, 2016
Grant date	—

Abstract

Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.

First claim

What is claimed is:

1 . Scrambling lane circuitry, comprising:
a first data input; a second data input; a first logic gate that receives signals from the first data input; a second logic gate that receives signals from the second data input; and a chain of additional logic gates connected in series, wherein the first logic gate also receives signals from a first additional logic gate in the chain, and wherein the second logic gate also receives signals from a second additional logic gate in the chain.

2 . The scrambling lane circuitry of claim 1 , wherein the first and second logic gates comprise logic exclusive-OR (XOR) gates.

3 . The scrambling lane circuitry of claim 1 , wherein the chain of additional logic gates comprises logic exclusive-OR (XOR) gates.

4 . The scrambling lane circuitry of claim 1 , further comprising:
a first multiplexer having a first input that is connected to the first data input, a second input that is connected to the first logic gate, and a third input that receives the signals from the first additional logic gate in the chain.

5 . The scrambling lane circuitry of claim 4 , further comprising:
a second multiplexer having a first input that is connected to the second data input, a second input that is connected to the second logic gate, and a third input that receives the signals from the second additional logic gate in the chain.

6 . The scrambling lane circuitry of claim 5 , further comprising:
a first flip-flop that is connected to an output of the first multiplexer and that has an output at which a first linear feedback shift register output signal is generated; and a second flip-flop that is connected to an output of the second multiplexer and that has an output at which a second linear feedback shift register output signal is generated.

7 . The scrambling lane circuitry of claim 6 , further comprising:
a third multiplexer that has a first input connected to the output of the first flip-flop, a second input that receives a first scrambling input signal, and an output that is coupled to the chain of additional logic gates.

8 . The scrambling lane circuitry of claim 7 , further comprising:
a fourth multiplexer that has a first input connected to the output of the second flip-flop, a second input that receives a second scrambling input signal, and an output that is coupled to the chain of additional logic gates.

9 . The scrambling lane circuitry of claim 8 , wherein the third and fourth multiplexers are configured in a first state to operate the scrambling lane circuitry in a cascade mode and are configured in a second state to operate the scrambling lane circuitry in a non-cascade mode.

10 . The scrambling lane circuitry of claim 1 , further comprising:
a third data input; and a third logic gate that receives signals from the third data input and from a third additional logic gate in the chain and that has an output at which a data output signal for the scrambling lane circuitry is provided.

11 . Scrambling lane circuitry, comprising:
a first group of multiplexers that receive scrambling input signals; and a chain of logic gates that are connected in series and that receive signals from the first group of multiplexers, wherein the number of logic gates in the chain of logic gates is greater than the number of multiplexers in the first group of multiplexers.

12 . The scrambling lane circuitry of claim 11 , further comprising:
a second group of multiplexers, wherein each multiplexer in the second group has more inputs than each multiplexer in the first group.

13 . The scrambling lane circuitry of claim 12 , further comprising:
flip-flops that receive signals from the second group of multiplexers and that output signals to the first group of multiplexers.

14 . The scrambling lane circuitry of claim 12 , wherein the number of multiplexers in the first group is equal to the number of multiplexers in the second group.

15 . The scrambling lane circuitry of claim 11 , further comprising:
a plurality of scrambling inputs; and a plurality of data inputs, wherein the number of data inputs is greater than the number of scrambling inputs.

16 . An integrated circuit comprising:
a plurality of shift register elements; a feedback XOR circuit tree; and programmable taps that are fewer in number than the plurality of shift register elements and that are coupled between a subset of the plurality of shift register elements and the feedback XOR circuit tree.

17 . The integrated circuit of claim 16 , wherein the programmable taps comprise a plurality of logic AND gates.

18 . The integrated circuit of claim 17 , further comprising:
a plurality of configuration elements that provides static control signals to the plurality of logic AND gates.

19 . The integrated circuit of claim 16 , further comprising:
a first multiplexer that has a first input that receives an data input signal, a second input that is coupled to an additional logic XOR gate, and a third input that is connected to the feedback XOR circuit tree.

20 . The integrated circuit of claim 19 , further comprising:
a second multiplexer that has a first input that receives a scrambling input signal, a second input that receives signals from the first multiplexer, and an output that is connected to the plurality of shift register elements.

Assignees

• Altera Corp

Inventors

• Wortman Curt
• Lee Chong H
• Ngo Huy

Classifications

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F13/12

  using hardware independent of the central processor, e.g. channel or peripheral processor · CPC title

• G06F3/00

  Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements · CPC title

• G06F5/00

  Methods or arrangements for data conversion without changing the order or content of the data handled · CPC title

• G11C7/1036

  using data shift registers · CPC title