Transmitter circuit, semiconductor apparatus and data transmission method

Patent metadata

Field	Value
Publication number	US-2016277043-A1
Application number	US-201615066900-A
Country	US
Kind code	A1
Filing date	Mar 10, 2016
Priority date	Mar 17, 2015
Publication date	Sep 22, 2016
Grant date	—

Abstract

The transmitter circuit according to one embodiment includes a pulse generating circuit generating a pulse signal based on edges of input data, a first output driver outputting, based on the pulse signal, a first output pulse signal according to one of the edges to a first end of an external insulating coupling element, a second output driver outputting, based on the pulse signal, a second output pulse signal according to other one of the edges to a second end of the insulating coupling element, and an output stop circuit stopping the first and second output pulse signals from being output for a prescribed period from when a power supply voltage is turned on.

First claim

What is claimed is:

1 . A transmitter circuit comprising:
a pulse generating circuit generating a pulse signal based on edges of input data; a first output driver outputting, based on the pulse signal, a first output pulse signal according to one of the edges to a first end of an external insulating coupling element; a second output driver outputting, based on the pulse signal, a second output pulse signal according to other one of the edges to a second end of the insulating coupling element; and an output stop circuit stopping the first and second output pulse signals from being output for a prescribed period from when a power supply voltage is turned on.

2 . The transmitter circuit according to claim 1 , wherein
the output stop circuit includes: a latch circuit sensing the turn-on of the power supply voltage and maintaining the stop of the output of the first and second output pulse signals; and a timer, wherein the latch circuit releases the stop of the output of the first and second output pulse signals in response to a signal output from the timer.

3 . The transmitter circuit according to claim 2 , wherein
the output stop circuit further includes first and second capacitor elements, the latch circuit has a first storage node connected to a power supply via the first capacitor element, and has a second storage node connected to a ground via the second capacitor element, the latch circuit retains voltages inverted from each other respectively at the first and second storage nodes, and the latch circuit releases the stop of the output of the first and second output pulse signals by the voltages retained at the first and second storage nodes transitioning in response to the signal output from the timer.

4 . The transmitter circuit according to claim 1 , wherein
the output stop circuit includes: first and second capacitor elements; an N-type transistor having its source connected to a ground and having its drain connected to a power supply via the first capacitor element; and a P-type transistor having its source connected to the power supply and having its drain connected to the ground via the second capacitor element, wherein the N-type transistor has its gate connected to the drain of the P-type transistor, and the P-type transistor has its gate connected to the drain of the N-type transistor, and the stop of the output of the first and second output pulse signals is released in accordance with a gate voltage of the N-type transistor and a gate voltage of the P-type transistor.

5 . The transmitter circuit according to claim 1 , wherein
the output stop circuit includes: a capacitor element connected to one of a power supply and a ground; and a resistor element connected to other one of the power supply and the ground, wherein the stop of the output of the first and second output pulse signals is released in accordance with a voltage of a connection node between the capacitor element and the resistor element.

6 . The transmitter circuit according to claim 1 , wherein
the output stop circuit stops the first and second output pulse signals from being output by stopping the pulse generating circuit from generating the pulse signal for a prescribed period from when the power supply voltage is turned on.

7 . A semiconductor apparatus comprising:
a transmitter circuit transmitting first and second output pulse signals based on input data; a receiver circuit receiving the first and second output pulse signals and reconstructing the input data; and a primary insulating coupling element and a secondary insulating coupling element electromagnetically coupling the transmitter circuit and the receiver circuit to each other, wherein the transmitter circuit includes: a pulse generating circuit generating a pulse signal based on edges of the input data; a first output driver outputting, based on the pulse signal, the first output pulse signal according to one of the edges to a first end of the primary insulating coupling element; a second output driver outputting, based on the pulse signal, the second output pulse signal according to other one of the edges to a second end of the primary insulating coupling element; and an output stop circuit stopping the first and second output pulse signals from being output for a prescribed period from when a power supply voltage is turned on.

8 . The semiconductor apparatus according to claim 7 , wherein
the output stop circuit includes: a latch circuit sensing the turn-on of the power supply voltage and maintaining the stop of the output of the first and second output pulse signals; and a timer, wherein the latch circuit releases the stop of the output of the first and second output pulse signals in response to a signal output from the timer.

9 . The semiconductor apparatus according to claim 8 , wherein
the output stop circuit further includes first and second capacitor elements, the latch circuit has a first storage node connected to a power supply via the first capacitor element, and has a second storage node connected to a ground via the second capacitor element, the latch circuit retains voltages inverted from each other respectively at the first and second storage nodes, and the latch circuit releases the stop of the output of the first and second output pulse signals by the voltages retained at the first and second storage nodes transitioning in response to the signal output from the timer.

10 . The semiconductor apparatus according to claim 7 , wherein
the output stop circuit includes: first and second capacitor elements; an N-type transistor having its source connected to a ground and having its drain connected to a power supply via the first capacitor element; and a P-type transistor having its source connected to the power supply and having its drain connected to the ground via the second capacitor element, wherein the N-type transistor has its gate connected to the drain of the P-type transistor, and the P-type transistor has its gate connected to the drain of the N-type transistor, and the stop of the output of the first and second output pulse signals is released in accordance with a gate voltage of the N-type transistor and a gate voltage of the P-type transistor.

11 . The semiconductor apparatus according to claim 7 , wherein
the output stop circuit includes: a capacitor element connected to one of a power supply and a ground; and a resistor element connected to other one of the power supply and the ground, wherein the stop of the output of the first and second output pulse signals is released in accordance with a voltage of a connection node between the capacitor element and the resistor element.

12 . The semiconductor apparatus according to claim 7 , wherein
the output stop circuit stops the first and second output pulse signals from being output by stopping the pulse generating circuit from generating the pulse signal for a prescribed period from when the power supply voltage is turned on.

13 . The semiconductor apparatus according to claim 7 , wherein
the primary insulating coupling element and the secondary insulating coupling element are coils respectively formed in two interconnection layers stacked in a top-bottom direction in a semiconductor chip.

14 . A data transmission method comprising:
generating a pulse signal based on edges of input data; outputting, based on the pulse signal, a first output pulse signal according to the edge to a first end of an insulating coupling element, and outputting a second output pulse signal according to other one of the edges to a second end o

Assignees

• Renesas Electronics Corp

Inventors

• Takeda Koichi
• Nagase Hirokazu
• Watanabe Shinpei

Classifications

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H04B1/40

  Circuits · CPC title

• H04B1/04 Primary

  Circuits · CPC title