Monolithic integrated photonics with lateral bipolar and bicmos

Patent metadata

Field	Value
Publication number	US-2016276807-A1
Application number	US-201514662590-A
Country	US
Kind code	A1
Filing date	Mar 19, 2015
Priority date	Mar 19, 2015
Publication date	Sep 22, 2016
Grant date	—

Abstract

After forming a first trench extending through a top semiconductor layer and a buried insulator layer and into a handle substrate of a semiconductor-on-insulator (SOI) substrate, a dielectric waveguide material stack including a lower dielectric cladding layer, a core layer and an upper dielectric cladding layer is formed within the first trench. Next, at least one lateral bipolar junction transistor (BJT), which can be a PNP BJT, an NPN BJT or a pair of complementary PNP BJT and NPN BJT, is formed in a remaining portion of the top semiconductor layer. After forming a second trench extending through the dielectric waveguide material stack to re-expose a portion of a bottom surface of the first trench, a laser diode is formed in the second trench.

First claim

What is claimed is:

1 . A semiconductor structure comprising
at least one electronic device located on a portion of a semiconductor-on-insulator (SOI) substrate, wherein the at least one electron device comprises at least one bipolar junction transistor (BJT); and photonic devices embedded within another portion of the SOI substrate, wherein the photonic devices comprise:
a dielectric waveguide comprising a lower dielectric cladding portion, a core portion present on the lower dielectric cladding portion, and an upper dielectric cladding potion present on the core portion; and
an optoelectronic device edge coupled to the dielectric waveguide, the optoelectronic device comprising an active layer laterally aligned to the core portion of the dielectric waveguide.

2 . The semiconductor structure of claim 1 , wherein the optoelectronic device is a laser diode, wherein said active layer is sandwiched between a lower semiconductor cladding layer and an upper semiconductor cladding layer.

3 . The semiconductor structure of claim 1 , wherein the at least one BJT comprises an intrinsic base laterally contacting an emitter and a collector and an extrinsic base present on the intrinsic base, wherein the intrinsic base, the emitter and the collector are located in a top semiconductor layer of the SOI substrate and vertically contact a buried insulator layer of the SOI substrate.

4 . The semiconductor structure of claim 3 , wherein the at least one BJT is an NPN BJT, wherein the intrinsic base of the NPN BJT is a p-type semiconductor region, the emitter and collector of the NPN BJT are heavily doped n-type semiconductor regions separated by the intrinsic base, and the extrinsic base of the NPN BJT is a heavily doped p-type semiconductor region.

5 . The semiconductor structure of claim 3 , wherein the at least one BJT is an PNP BJT, wherein the intrinsic base of the PNP BJT is an n-type semiconductor region, the emitter and collector of the PNP BJT are heavily doped p-type semiconductor regions separated by the intrinsic base, and the extrinsic base of the PNP BJT is a heavily doped n-type semiconductor region.

6 . The semiconductor structure of claim 3 , wherein the at least one BJT comprises complementary BJTs, wherein the complementary BJTs comprises a PNP BJT located in a first region of the top semiconductor layer, and an NPN BJT located in a second region of the top semiconductor layer.

7 . The semiconductor structure of claim 6 , wherein the at least one electron device further comprises complementary metal-oxide-semiconductor (CMOS) transistors , wherein the CMOS transistors comprise a p-type metal-oxide-semiconductor (PMOS) transistor located in a third region of the top semiconductor layer and comprising a first channel portion laterally contacting by first source/drain regions, and a first gate structure present on the first channel portion, and an n-type metal-oxide-semiconductor (NMOS) transistor located in a fourth region of the top semiconductor layer and comprising a second channel portion laterally contacting by second source/drain regions, and a second gate structure present on the second channel portion.

8 . The semiconductor structure of claim 2 , wherein the lower semiconductor cladding layer is present on a compound semiconductor buffer layer, the compound semiconductor buffer layer present on a compound semiconductor seed layer in contact with a sub-surface of a handle substrate of the SOI substrate.

9 . The semiconductor structure of claim 1 , wherein the lower dielectric cladding layer portion vertically contacts the sub-surface of the handle substrate of the SOI substrate.

10 . The semiconductor structure of claim 1 , wherein the SOI substrate further comprising a lower germanium-containing layer present between a buried insulator layer and a handle substrate of the SOI substrate.

11 . The semiconductor structure of claim 10 , wherein the buried insulator layer is a stack of a first dielectric layer present on the lower germanium-containing layer, a second dielectric layer present on the first dielectric layer, and a third dielectric layer present on the second dielectric layer.

12 . A method of forming a semiconductor structure comprising:
forming a first trench within a semiconductor-on-insulator (SOI) substrate, the first trench extending through a top semiconductor layer of the SOI substrate and a buried insulator layer of the SOI substrate and into a handle substrate of the SOI substrate; forming a dielectric waveguide material stack in the first trench; forming at least one electronic device in the top semiconductor layer, wherein the at least one electronic device comprises at least one bipolar junction transistor (BJT); forming a second trench extending through a portion of the dielectric waveguide material stack, the second trench re-exposing a portion of the bottom surface of the first trench; epitaxially depositing a compound semiconductor seed layer on the exposed portion of the bottom surface of the first trench; epitaxially depositing a compound semiconductor buffer layer on the compound semiconductor seed layer; and forming an optoelectronic device on the compound semiconductor buffer layer within the second trench.

13 . The method of claim 12 , wherein the forming the at least one electronic device in the top semiconductor layer comprises forming a PNP BJT in a first device region of the top semiconductor layer and an NPN BJT in a second device region of the top semiconductor layer.

14 . The method of claim 13 , wherein the forming the at least one electronic device in the top semiconductor layer comprises:
forming the first and the second device regions laterally surrounded by shallow trench isolation (STI) structures in the top semiconductor layer; implanting n-type dopants to the first device region of the top semiconductor layer to provide an n-type semiconductor region; implanting p-type dopants to the second device region of the top semiconductor layer to provide a p-type semiconductor region; forming a semiconductor layer over the first device region and the second device region of the top semiconductor layer; patterning the semiconductor layer to form a first semiconductor layer portion over the n-type semiconductor region and a second semiconductor layer portion over the p-type semiconductor region; implanting n-type dopants to the first semiconductor layer portion to provide a first extrinsic base; implanting p-type dopants to the second semiconductor layer portion to provide a second extrinsic base; forming a dielectric spacer on each sidewall of the first extrinsic base and the second extrinsic base; implanting p-type dopants to portions of the top semiconductor layer in the first device region that are not covered by the first extrinsic base or the dielectric spacers; and implanting n-type dopants to portions of the top semiconductor layer in the second device region that are not covered by the second extrinsic base or the gate spacers while masking the first device region.

15 . The method of claim 12 , wherein the forming the at least one electronic device in the top semiconductor layer comprises forming complementary metal-oxide-semiconductor (CMOS) transistors in a first device region of the top semiconductor layer and complementary bipolar junction transistors (BJTs) in a second device region of the top semiconductor layer, wherein the CMOS transistors comprise a p-type metal-oxide-semiconductor (PMOS) transistor located in a first sub-region of the first device region and an n-type metal-oxide-semiconductor (NMOS) transistor loc

Assignees

• IBM

Inventors

• Cai Jin
• Leobandung Effendi
• Li Ning
• Ning Tak H
• Plouchart Jean-Olivier
• Sadana Devendra K

Classifications

• H01S5/021

  Silicon based substrates · CPC title

• H01S5/0261

  Non-optical elements, e.g. laser driver components, heaters (H01S5/0265 takes precedence) · CPC title

• G02B6/12004

  Combinations of two or more optical elements · CPC title

• H01S5/026 Primary

  Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers (stabilisation of output H01S5/06) · CPC title

• G02B6/42

  Coupling light guides with opto-electronic elements · CPC title