Package structures having integrated waveguides for high speed communications between package components

Patent metadata

Field	Value
Publication number	US-2016276729-A1
Application number	US-201514750033-A
Country	US
Kind code	A1
Filing date	Jun 25, 2015
Priority date	Mar 19, 2015
Publication date	Sep 22, 2016
Grant date	—

Abstract

Embodiments include package structures having integrated waveguides to enable high data rate communication between package components. For example, a package structure includes a package substrate having an integrated waveguide, and first and second integrated circuit chips mounted to the package substrate. The first integrated circuit chip is coupled to the integrated waveguide using a first transmission line to waveguide transition, and the second integrated circuit chip is coupled to the integrated waveguide using a second transmission line to waveguide transition. The first and second integrated circuit chips are configured to communicate by transmitting signals using the integrated waveguide within the package carrier.

First claim

1 . A semiconductor wafer, comprising:
a bulk substrate layer; an active silicon layer; a BEOL (back end of line) layer formed on the active layer; an integrated waveguide formed, at least in part, in the bulk substrate layer; a first transmission line to waveguide transition; a second transmission line to waveguide transition; a first integrated circuit coupled to the integrated waveguide via the first transmission line to waveguide transition; and a second integrated circuit coupled to the integrated waveguide via the second transmission line to waveguide transition; wherein the first and second integrated circuits of the semiconductor wafer are configured to communicate by transmitting signals using the integrated waveguide.

2 . The semiconductor wafer of claim 1 , wherein the integrated waveguide comprises:
a first metallic plate patterned from a first metallization layer: a second metallic plate patterned from a second metallization layer; and sidewalls disposed between the first and second metallic plates; wherein the first metallization layer comprises a metallization layer of the BEOL layer; wherein the second metallization layer is formed on the bulk substrate layer; wherein the sidewalls comprise a series of conductive through-silicon vias that are formed through the active layer and the bulk substrate layer connecting the first and second metallic plates and wherein at least a portion of the first and second transmission line to waveguide transitions are formed from the first metallization layer.

3 . The semiconductor wafer of claim 2 , wherein the bulk substrate layer comprises a high resistivity silicon substrate.

4 . A package structure comprising the semiconductor wafer of claim 1 , wherein the package structure comprises a package carrier with the semiconductor wafer mounted on a surface of the package carrier using an array of micro bump connections between the BEOL layer and the surface of the package carrier.

5 . A package structure comprising the semiconductor wafer of claim 1 , wherein the package structure comprises a package carrier with the semiconductor wafer mounted on a surface of the package carrier using an array of micro bump connections between the bulk substrate layer and the surface of the package carrier, wherein the bulk substrate layer comprises a plurality of through-silicon vias to provide electrical interconnects between the package carrier and the BEOL layer.

6 . The semiconductor wafer of claim 1 , wherein the first and second transmission line to waveguide transitions comprise one of a microstrip to waveguide transition, a coplanar waveguide to waveguide transition, a stripline to waveguide transition, and a slotted feed to waveguide transition.

7 . The semiconductor wafer of claim 2 , wherein a spacing S between the conductive vias that form the sidewalls of the integrated waveguide is less than or equal to about one-quarter (¼) of an operating wavelength of the integrated waveguide.

8 . The semiconductor wafer of claim 2 , wherein a height H of the integrated waveguide is defined by a distance between the first and second metallic plates, wherein a width W of the integrated waveguide is defined by a distance between opposing sidewalls of the integrated waveguide device, and wherein the width W is greater than 2×H.

9 . The semiconductor wafer of claim 8 , wherein the width W is approximately one-half (½) an operating wavelength of the integrated waveguide.

10 . The semiconductor wafer of claim 2 , wherein, at least one of the first metallic plate and the second metallic plate of the integrated waveguide comprises a ground plane of the BEOL layer.

11 . A semiconductor device, comprising:
a semiconductor wafer comprising:
an integrated waveguide;
a first integrated circuit die; and
a second integrated circuit die;
wherein the first and second integrated dies of the semiconductor wafer are coupled to the integrated waveguide of the semiconductor wafer; and wherein the first and second integrated circuit dies of the semiconductor wafer are configured to communicate by transmitting signals using the integrated waveguide of the semiconductor wafer.

12 . The semiconductor device of claim 11 , wherein the semiconductor wafer comprises a SO 1 (silicon on insulator) wafer.

13 . The semiconductor device of claim 11 , wherein the semiconductor wafer further comprises first and second transmission line to waveguide transitions to couple the first and second integrated circuit dies, respectively, to the integrated waveguide, wherein the first and second transmission line to waveguide transitions comprise one of a microstrip to waveguide transition, a coplanar waveguide to waveguide transition, a stripline to waveguide transition, and a slotted feed to waveguide transition.

14 . The semiconductor device of claim 11 , wherein the integrated waveguide comprises:
a first metallic plate formed as part of a BEOL (back-end-of-line) layer of the semiconductor wafer; a second metallic plate formed on a back side surface of the semiconductor wafer; sidewalk disposed between the first and second metallic plates, wherein the sidewalls comprise a series of conductive vias that are formed through the semiconductor wafer connecting the first and second metallic plates.

15 . The semiconductor device of claim 14 , wherein a spacing S between the conductive vias that form the sidewalls of the integrated waveguide is less than or equal to about one-quarter (¼) of an operating wavelength of the integrated waveguide.

16 . The semiconductor device of claim 14 , wherein a height H of the integrated waveguide is defined by a distance between the first and second metallic plates, wherein a width W of the integrated waveguide is defined by a distance between opposing sidewalk of the integrated waveguide, and wherein the width W is greater than 2×H.

17 . The semiconductor device of claim 16 , wherein the width W is approximately one-half (½) an operating wavelength of the integrated waveguide.

18 . The semiconductor device of claim 14 , wherein the first metallic plate of the integrated waveguide comprises a ground plane of the BEOL layer.

Assignees

• IBM

Inventors

• Dang Bing
• Liu Duixian
• Plouchart Jean-Olivier
• Valdes-Garcia Alberto

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/247

  Dispositions of multiple bumps · CPC title

• H10W44/248

  for antennas · CPC title

• H10W44/219

  characterised by transitions between different types of waveguides · CPC title