Package structures having integrated waveguides for high speed communications between package components

Patent metadata

Field	Value
Publication number	US-2016276727-A1
Application number	US-201514662610-A
Country	US
Kind code	A1
Filing date	Mar 19, 2015
Priority date	Mar 19, 2015
Publication date	Sep 22, 2016
Grant date	—

Abstract

Embodiments include package structures having integrated waveguides to enable high data rate communication between package components. For example, a package structure includes a package substrate having an integrated waveguide, and first and second integrated circuit chips mounted to the package substrate. The first integrated circuit chip is coupled to the integrated waveguide using a first transmission line to waveguide transition, and the second integrated circuit chip is coupled to the integrated waveguide using a second transmission line to waveguide transition. The first and second integrated circuit chips are configured to communicate by transmitting signals using the integrated waveguide within the package carrier.

First claim

1 . A package structure, comprising:
a package substrate comprising an integrated waveguide; and a first integrated circuit chip and a second integrated circuit chip mounted to the package substrate; wherein the first integrated circuit chip is coupled to the integrated waveguide using a first transmission line to waveguide transition; wherein the second integrated circuit chip is coupled to the integrated waveguide using a second transmission line to waveguide transition; and wherein the first and second integrated circuit chips are configured to communicate by transmitting signals using the integrated waveguide of the package substrate.

2 . The package structure of claim 1 , wherein the package substrate comprises:
a planar substrate; and a first metallization layer and a second metallization layer formed on opposite surfaces of the planar substrate; wherein at least a portion of the first and second transmission line to waveguide transitions are formed from at least one of the first and second metallization layers; and wherein the integrated waveguide comprises:
a first metallic plate patterned from the first metallization layer;
a second metallic plate patterned from the second metallization layer; and
sidewalls disposed between the first and second metallic plates;
wherein the sidewalls comprise a series of conductive vias that are formed through the planar substrate connecting the first and second metallic plates.

3 . The package structure of claim 2 , wherein the planar substrate comprises at least a first substrate and a second substrate which are bonded together, wherein the first substrate comprise a first probe element that forms part of the first transmission line to waveguide transition, and a second probe element that forms part of the second transmission line to waveguide transition, wherein the first and second probe elements comprise conductive buried vias formed in the first substrate.

4 . The package structure of claim 1 , wherein the package substrate comprises a glass substrate.

5 . The package structure of claim 1 , wherein the package substrate comprises a high resistivity silicon substrate.

6 . The package structure of claim 1 , further comprising an application board;
wherein the package substrate comprising the integrated waveguide is mounted to the application board such that the package substrate serves as an interposer between the application board and the first and second integrated circuit chips; wherein the package substrate comprises a plurality of conductive vias formed through the package substrate, and wiring patterns formed on surfaces of the package substrate; and wherein the conductive vias and the wiring patterns of the package substrate are configured to route low frequency signals between the first and second integrated circuit chips and between the application board and the first and second integrated circuit chips, and to distribute DC power from the application board to the first and second integrated circuit chips.

7 . The package structure of claim 1 , further comprising an application board;
wherein active surfaces of the first and second integrated circuit chips are mounted to the package substrate comprising the integrated waveguide; wherein the application board is mounted to inactive surfaces of the first and second integrated circuit chips, such that the first and second integrated circuit chips are disposed between the application board and the package substrate; and wherein the first and second integrated circuit chips comprise through-silicon vias that are formed in bulk substrate layers of the first and second integrated circuit chips, wherein the through-silicon vias provide electrical connections between the application board and BEOL (back end of line) structures of the first and second integrated circuit chips.

8 . The package structure of claim 1 , further comprising an application board;
wherein the first and second integrated circuit chips each comprise a silicon-on-insulator (SOL) substrate, wherein the SOI substrate comprises a BEOL (back end of line structure), an active silicon layer, and a buried oxide layer; wherein the buried oxide layers of the first and second integrated circuit chips are bonded to the package substrate comprising the integrated waveguide; wherein the application board is mounted to the BEOL structures of the first and second integrated circuit chips, such that the first and second integrated circuit chips are disposed between the application board and the package substrate; and wherein at least a portion of the first and second transmission line to waveguide transitions comprise metallization structures that are formed in regions of the active silicon and buried oxide layers.

9 . The package structure of claim 1 , wherein the package substrate comprises an application board in which the integrated waveguide is formed.

10 . The package structure of claim 1 , further comprising an antenna package mounted to the package substrate, wherein the package substrate comprises an integrated power combiner structure connecting the antenna package and the first and second integrated circuit chips, wherein the integrated power combiner comprises integrated waveguide structures integrally formed in the package substrate.

11 . The package structure of claim 1 , further comprising an antenna package mounted to the package substrate, wherein the package substrate comprises an integrated power divider structure connecting the antenna package and the first and second integrated circuit chips, wherein the integrated power divider comprises integrated waveguide structures integrally formed in the package substrate.

12 . The package structure of claim 1 , further comprising a waveguide interface connected to the package substrate, wherein the waveguide interface is configured to couple to a metallic waveguide or a dielectric waveguide, wherein the package substrate comprises a second integrated waveguide connecting the waveguide interface to at least one of the first and second integrated circuit chips.

13 . The package structure of claim 1 , wherein the first and second transmission line to waveguide transitions comprise one of a microstrip to waveguide transition, a coplanar waveguide to waveguide transition, a sulphite to waveguide transition, and a slotted feed to waveguide transition.

14 . The package structure of claim 1 , wherein at least one of the first and second transmission line to waveguide transitions comprises a slotted feed to waveguide transition, wherein the slotted feed to waveguide transition comprises:
first and second slots patterned adjacent to each other in an edge region of a first metallic plate of the integrated waveguide; wherein first length portions of the first and second slots extend in parallel from an edge of the first metallic plate; wherein second length portions of the first and second slots extend at diverging angles from ends of the respective first length portions; wherein a portion of the first metallic plate between the first and second slots provides a signal line connection to the slotted feed to waveguide transition; and wherein portions of the first metallic plate on opposite sides of the first and second slots provide ground connections to the slotted feed to waveguide transition.

15 .- 19 . (canceled)

20 . (canceled)

21 . The package structure of claim 2 , wherein a spacing S between the conductive vias that form the sidewalls of the integrated waveguide is less than or equal to about one-quarter (¼) of an operat

Assignees

• IBM

Inventors

• Dang Bing
• Liu Duixian
• Plouchart Jean-Olivier
• Valdes-Garcia Alberto

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/247

  Dispositions of multiple bumps · CPC title

• H10W44/248

  for antennas · CPC title

• H10W44/219

  characterised by transitions between different types of waveguides · CPC title