Semiconductor device and manufacturing method thereof

US2016276489A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016276489-A1
Application numberUS-201615168291-A
CountryUS
Kind codeA1
Filing dateMay 31, 2016
Priority dateApr 16, 2012
Publication dateSep 22, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An object is to suppress conducting-mode failures of a transistor that uses an oxide semiconductor film and has a short channel length. A semiconductor device includes a gate electrode 304, a gate insulating film 306 formed over the gate electrode, an oxide semiconductor film 308 over the gate insulating film, and a source electrode 310 a and a drain electrode 310 b formed over the oxide semiconductor film. The channel length L of the oxide semiconductor film is more than or equal to 1 μm and less than or equal to 50 μm. The oxide semiconductor film has a peak at a rotation angle 2θ in the vicinity of 31° in X-ray diffraction measurement.

First claim

Opening claim text (preview).

1 . A semiconductor device comprising: an oxide semiconductor layer, wherein a length of a channel formed in the oxide semiconductor layer is more than or equal to 1 μm and less than or equal to 50 μm, and wherein a diffraction intensity of the oxide semiconductor layer in X-ray diffraction measurement has a peak at a rotation angle 2θ of more than or equal to 30° and less than or equal to 32°. 2 . The semiconductor device according to claim 1 further comprising: a gate electrode; a gate insulating layer over the gate electrode; and a source electrode and a drain electrode over the oxide semiconductor layer, wherein the oxide semiconductor layer is over the gate insulating layer. 3 . The semiconductor device according to claim 1 , wherein the length of the channel is less than 5 μm. 4 . The semiconductor device according to claim 1 , wherein a band gap of the oxide semiconductor layer is more than or equal to 3.1 eV. 5 . The semiconductor device according to claim 1 , wherein the oxide semiconductor layer includes at least one oxide selected from the group consisting of indium oxide, zinc oxide, gallium oxide, tin oxide and a combination thereof. 6 . The semiconductor device according to claim 1 , wherein the oxide semiconductor layer is an In—Ga—Zn-based oxide semiconductor layer. 7 . The semiconductor device according to claim 1 , wherein the oxide semiconductor layer includes a crystal part, and wherein a c-axis of the crystal part is aligned in a direction substantially parallel to a normal vector of a surface on which the oxide semiconductor layer is formed. 8 . A semiconductor device comprising: an oxide semiconductor layer, wherein a length of a channel formed in the oxide semiconductor layer is more than or equal to 1 μm and less than or equal to 50 μm, wherein the oxide semiconductor layer includes a crystal part, and wherein a c-axis of the crystal part is aligned in a direction substantially parallel to a normal vector of a surface on which the oxide semiconductor layer is formed. 9 . The semiconductor device according to claim 8 further comprising: a gate electrode; a gate insulating layer over the gate electrode; and a source electrode and a drain electrode over the oxide semiconductor layer, wherein the oxide semiconductor layer is over the gate insulating layer. 10 . The semiconductor device according to claim 8 , wherein the length of the channel is less than 5 μm. 11 . The semiconductor device according to claim 8 , wherein the oxide semiconductor layer is an In—Ga—Zn-based oxide semiconductor layer. 12 . The semiconductor device according to claim 1 further comprising: a substrate; and a base insulating film between the substrate and the oxide semiconductor layer. 13 . The semiconductor device according to claim 12 , wherein the base insulating film is one of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film and an aluminum oxide film. 14 . The semiconductor device according to claim 13 , wherein the base insulating film is the aluminum oxide film, and wherein a density of the aluminum oxide film is 3.2 g/cm 3 or more. 15 . The semiconductor device according to claim 13 , wherein the base insulating film is the aluminum oxide film, and wherein an amount of water (H 2 O) released from the aluminum oxide film is less than or equal to 5×10 15 atoms/cm 3 . 16 . The semiconductor device according to claim 13 , wherein the base insulating film is the aluminum oxide film, and wherein an amount of hydrogen (H 2 ) released from the aluminum oxide film is less than or equal to 5×10 15 atoms/cm 3 .

Assignees

Inventors

Classifications

  • the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides · CPC title

  • Subject matter not provided for in other groups of this subclass · CPC title

  • characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

  • having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

  • of thin-film transistors [TFT] · CPC title

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What does patent US2016276489A1 cover?
An object is to suppress conducting-mode failures of a transistor that uses an oxide semiconductor film and has a short channel length. A semiconductor device includes a gate electrode 304, a gate insulating film 306 formed over the gate electrode, an oxide semiconductor film 308 over the gate insulating film, and a source electrode 310 a and a drain electrode 310 b formed over th…
Who is the assignee on this patent?
Okazaki Kenichi, Yokoyama Masatoshi, Sakakura Masayuki, and 7 more
What technology area does this patent fall under?
Primary CPC classification H10D30/6755. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Sep 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).