Conductive cap for metal-gate transistor

Patent metadata

Field	Value
Publication number	US-2016276455-A1
Application number	US-201514661953-A
Country	US
Kind code	A1
Filing date	Mar 18, 2015
Priority date	Mar 18, 2015
Publication date	Sep 22, 2016
Grant date	—

Abstract

A semiconductor device includes a gate region, a conductive cap, and an interconnect. The gate region (e.g., a metal-gate transistor) includes a metal gate region and a high dielectric constant (high-K) gate dielectric region. The conductive cap is disposed on a surface of the metal gate region and on a surface of the high-K gate dielectric region, and the interconnect is disposed on the conductive cap. The conductive cap includes a conductive material that electrically connects the gate region to the interconnect.

First claim

1 . A semiconductor device comprising:
a gate region, wherein the gate region includes a metal gate region and a high dielectric constant (high-K) gate dielectric region; a conductive cap disposed on a surface of the metal gate region and on a surface of the high-K gate dielectric region; and an interconnect disposed on the conductive cap, wherein the conductive cap includes a conductive material to electrically connect the gate region to the interconnect.

2 . The semiconductor device of claim 1 , wherein the interconnect includes copper (Cu), and wherein the conductive cap substantially inhibits diffusion of the copper (Cu) from the interconnect into the gate region.

3 . The semiconductor device of claim 2 , wherein the interconnect further includes a liner material that is positioned between the copper (Cu) and the conductive cap.

4 . The semiconductor device of claim 1 , wherein the metal gate region includes a work function material disposed between a gate metal of the metal gate region and the high-K gate dielectric region.

5 . The semiconductor device of claim 4 , wherein the conductive cap substantially inhibits diffusion of the work function material from the metal gate region into the interconnect.

6 . The semiconductor device of claim 1 , wherein the conductive material of the conductive cap includes tungsten (W), cobalt (Co), or tantalum (Ta).

7 . The semiconductor device of claim 1 , wherein a gate metal of the metal gate region includes aluminum (Al) or tungsten (W).

8 . The semiconductor device of claim 1 , wherein a surface of a metal gate of the metal gate region is substantially parallel to the surface of the high-K gate dielectric region.

9 . The semiconductor device of claim 8 , wherein a first distance from the interconnect to the surface of the gate metal of the metal gate region is different from a second distance from the interconnect to the surface of the high-K gate dielectric region.

10 . The semiconductor device of claim 1 , wherein the gate region is disposed within a channel of an inter-layer dielectric (ILD) layer, wherein the ILD layer is disposed on a surface of a substrate, and wherein the channel has a channel length that is less than 20 nanometers (nm).

11 . The semiconductor device of claim 10 , further comprising a spacer layer disposed within the channel of the ILD layer, wherein the spacer layer is between the gate region and the ILD layer.

12 . A method of fabricating a semiconductor device, the method comprising:
forming a gate region on a substrate, wherein the gate region includes a metal gate region and a high dielectric constant (high-K) gate dielectric region; removing a first portion of material from the metal gate region and a second portion of material from the high-K gate dielectric region; forming a cap on a surface of the metal gate region and on a surface of the high-K gate dielectric region; and forming an interconnect on the cap, wherein the cap includes a conductive material.

13 . The method of claim 12 , wherein forming the gate region on the substrate includes:
etching a recess in an inter-layer dielectric (ILD) layer to expose a surface of the substrate; forming a high-K layer on the surface of the substrate; forming a work function layer on the high-K layer; and forming a metal gate layer on the work function layer.

14 . The method of claim 13 , wherein forming the metal gate layer includes depositing an aluminum (Al) layer or a tungsten (W) layer on the work function layer.

15 . The method of claim 13 , wherein etching the recess in the ILD layer exposes a channel overlying the substrate, and wherein the channel has a channel length that is less than 20 nanometers (nm).

16 . The method of claim 12 , wherein removing the first portion of material from the metal gate region and the second portion of material from the high-K gate dielectric region includes etching the metal gate region and the high-K gate dielectric region.

17 . The method of claim 16 , wherein etching the metal gate region and the high-K gate dielectric region includes:
etching a metal gate of the metal gate region at a first etch rate; and etching the high-K gate dielectric region at a second etch rate.

18 . The method of claim 17 , wherein the first etch rate and the second etch rate are substantially the same, resulting in the gate region having a substantially flat surface.

19 . The method of claim 17 , wherein the first etch rate is different from the second etch rate, resulting in a surface of the gate metal being disposed at a different distance from the interconnect than the surface of the high-K gate dielectric region.

20 . The method of claim 12 , wherein forming the interconnect on the cap includes:
forming an inter-layer dielectric (ILD) layer; etching a recess in the ILD layer to expose a surface of the cap; and depositing a copper (Cu) layer on the surface of the cap.

21 . The method of claim 12 , wherein forming the interconnect on the cap includes:
forming an inter-layer dielectric (ILD) layer; etching a recess in the ILD layer to expose a surface of the cap; depositing a liner layer on the surface of the cap; and depositing a copper (Cu) layer on the surface of the liner layer.

22 . The method of claim 12 , wherein forming the cap on the gate region includes depositing a tungsten (W) layer, a cobalt (Co) layer, or a tantalum (Ta) layer on the metal gate region and on the high-K gate dielectric region.

23 . The method of claim 12 , further comprising removing a portion of material from the cap prior to forming the interconnect on the cap.

24 . The method of claim 23 , wherein the portion of material from the cap is removed by chemical-mechanical planarization.

25 . An apparatus comprising:
means for gating a channel of a semiconductor device, the means for gating including a metal gate region and a high dielectric constant (high-K) gate dielectric region; means for capping the metal gate region and the high-K gate dielectric region; and means for interconnecting the means for capping to circuitry of the semiconductor device.

26 . The apparatus of claim 25 , wherein the means for interconnecting includes copper (Cu), and wherein the means for capping includes means for inhibiting solid-state diffusion of copper (Cu) from the means for interconnecting into the means for gating.

27 . The apparatus of claim 25 , wherein the means for capping includes means for inhibiting solid-state diffusion of work function material from the metal gate region into the means for interconnecting.

28 . The apparatus of claim 25 , wherein the channel has a channel length that is less than 20 nanometers (nm).

29 . A non-transitory computer-readable medium comprising instructions for forming a semiconductor device, the instructions when executed by a processor, cause the processor to:
initiate formation of a gate region on a substrate, wherein the gate region includes a metal gate region and a high dielectric constant (high-K) gate dielectric region; initiate removal of a first portion of material from the metal gate region and a second portion of material from the high-K gate dielectric region; initiate formation of a cap on a surface of the metal gate region and on a surface of the high-K gate dielectric region; and initiate formation of an in

Assignees

• Qualcomm Inc

Inventors

• Yang Haining
• Song Stanley Seungchul

Classifications

• H10P50/264

  by chemical means · CPC title

• H10D64/01354

  passivation or protection of the electrode, e.g. using re-oxidation · CPC title

• H10D64/01324

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H10D64/01316

  the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title