Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016276385-A1
Application number	US-201615167348-A
Country	US
Kind code	A1
Filing date	May 27, 2016
Priority date	Mar 15, 2007
Publication date	Sep 22, 2016
Grant date	—

Abstract

A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.

First claim

What is claimed is:

1 . A device comprising:
a semiconductor substrate having oppositely facing first and second surfaces; a pad electrode; a first opening in the semiconductor substrate extending from the second surface toward the pad electrode; a second opening extending from the first opening to a sealing layer, the first opening having a diameter larger than that of the second opening; an insulating layer in at least the first opening; and conductive material in the first and second openings and electrically connected to the pad electrode.

2 . The device of claim 1 , wherein the second opening has a smallest diameter that is 0.7 times or less than a largest diameter of the first opening.

3 . The device of claim 2 , wherein the smallest diameter of the second opening is 0.5 times or less than the largest diameter of the first opening.

4 . The device of claim 1 , further comprising:
a package substrate facing the first surface of the semiconductor substrate; and an electronic element on the first surface, wherein, the sealing layer is between a peripheral portion of the electronic element, and the package substrate and the sealing layer are configured to seal the electronic element.

5 . The device of claim 4 , wherein the electronic element is a solid-state image sensor.

6 . The device of claim 1 , wherein the second opening is filled with the conductive material.

7 . The device of claim 1 , wherein the pad electrode is on the first surface.

8 . The device of claim 1 , wherein a depth of the first opening is 0.5 times or more and 0.9 times or less than a thickness of the semiconductor substrate.

9 . The device of claim 6 , wherein a thickness of the conductive material in the second opening is 0.1 times or more than a thickness of the semiconductor substrate.

10 . A device comprising:
a semiconductor substrate having oppositely facing first and second surfaces; a pad electrode; a first opening extending from the second surface toward the pad electrode; a second opening extending from the first opening to a sealing layer, the first opening having a diameter larger than that of the second opening; an insulating layer in at least the first opening; and conductive material in the first and second openings and electrically connected to the pad electrode, wherein the second opening is filled with the conductive material such that a thickness of the conductive material in the second opening is 0.1 times or more than a thickness of the semiconductor substrate.

11 . The device of claim 10 , wherein the second opening has a smallest diameter that is 0.7 times or less than a largest diameter of the first opening.

12 . The device of claim 11 , wherein the smallest diameter of the second opening is 0.5 times or less than the largest diameter of the first opening.

13 . The device of claim 10 , further comprising:
a package substrate facing the first surface of the semiconductor substrate; and an electronic element on the first surface, wherein, the sealing layer is between a peripheral portion of the electronic element and the package substrate, and the sealing layer is configured to seal the electronic element.

14 . The device of claim 13 , wherein the electronic element is a solid-state image sensor.

15 . The device of claim 10 , wherein the pad electrode is on the first surface.

16 . The device of claim 10 , wherein a depth of the first opening is 0.5 times or more and 0.9 times or less than a thickness of the semiconductor substrate.

Assignees

• Sony Corp

Inventors

• Nabe Yoshihiro
• Asami Hiroshi `
• Takaoka Yuji
• Harada Yoshimichi

Classifications

• H10W20/216

  characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title