High Voltage ESD Protection Apparatus

Patent metadata

Field	Value
Publication number	US-2016276334-A1
Application number	US-201615165832-A
Country	US
Kind code	A1
Filing date	May 26, 2016
Priority date	Sep 23, 2011
Publication date	Sep 22, 2016
Grant date	—

Abstract

A device comprises a high voltage n well and a high voltage p well over a buried layer, a first low voltage n well over the high voltage n well, wherein a bottom portion of the first low voltage n well is surrounded by the high voltage n well, an N+ region over the first low voltage n well, a second low voltage n well and a low voltage p well over the high voltage p well, a first P+ region over the second low voltage n well and a second P+ region over the low voltage p well.

First claim

What is claimed is:

1 . An apparatus comprising:
an NPN transistor having
a collector formed by a N+ region, a first low voltage n well and a high voltage n well;
a base formed by a first P+ region, a low voltage p well with a first doping density and a high voltage p well with a second doping density; and
an emitter formed by a second low voltage n well; and
a diode formed by a P+ region and the second low voltage n well, wherein:
the P+ region extends from a first isolation region to a second isolation region;
the P+ region is formed on the second low voltage n well; and
a top surface of the P+ region is level with a top surface of the N+ region.

2 . The apparatus of claim 1 , wherein:
a bottom surface of the second low voltage n well is level with a bottom surface of the first low voltage n well.

3 . The apparatus of claim 1 , wherein:
a bottom surface of the second low voltage n well is level with a bottom surface of the low voltage p well.

4 . The apparatus of claim 1 , wherein:
the N+ region is formed over the first low voltage n well; and the first low voltage n well is formed over the high voltage n well.

5 . The apparatus of claim 1 , wherein:
a breakdown voltage of the diode is about 10 V.

6 . The apparatus of claim 1 , wherein:
a bottom surface of the P+ region is higher than bottom surfaces of the first isolation region and the second isolation region.

7 . The apparatus of claim 1 , wherein:
the first doping density is substantially higher than the second doping density.

8 . The apparatus of claim 1 , wherein:
the diode and the NPN transistor are connected in series.

9 . A device comprising:
a high voltage n well and a high voltage p well over a buried layer; a first low voltage n well over the high voltage n well, wherein a bottom portion of the first low voltage n well is surrounded by the high voltage n well; a N+ region over the first low voltage n well; a second low voltage n well and a low voltage p well over the high voltage p well; a first P+ region over the second low voltage n well; and a second P+ region over the low voltage p well, wherein:
the N+ region and the first P+ region are separated by a first isolated region; and
the first P+ region and the second P+ region are separated by a second isolated region.

10 . The device of claim 9 , wherein:
the N+ region is a collector of a transistor; the second low voltage n well is an emitter of the transistor; and the second P+ region is a base of the transistor.

11 . The device of claim 10 , wherein:
the second low voltage n well and the first P+ region form a diode.

12 . The device of claim 11 , wherein:
the transistor and the diode are connected in series.

13 . The device of claim 12 , wherein:
a cathode of the diode is directly connected to the emitter of the transistor.

14 . The device of claim 9 , further comprising a third isolation region and a fourth isolation region, wherein:
the N+ region is formed between the first isolation region and the third isolation region; the first P+ region is formed between the first isolation region and the second isolation region; and the second P+ region is formed between the second isolation region and the fourth isolation region.

15 . A circuit comprising:
an integrated circuit having an I/O terminal; and a first electrostatic discharge protection device comprising
a diode formed by a first P+ region and an emitter of a transistor, wherein the first P+ region extends from a sidewall of a first isolation region to a sidewall of a second isolation region, and wherein an upper portion of the emitter is between the first isolation region and the second isolation region; and
the transistor having a collector formed by an N+ region, a base formed by a second P+ region, a low voltage p well and the emitter formed by a first low voltage n well, wherein:
the diode and the transistor are connected in series; and wherein
the diode and the transistor are coupled between the I/O terminal and ground.

16 . The circuit of claim 15 , where:
the transistor is an NPN transistor having the emitter coupled to a cathode of the diode.

17 . The circuit of claim 15 , where:
the collector of the transistor is connected to a first pad; and an anode of the diode is connected to a second pad.

18 . The circuit of claim 17 , wherein:
the first pad is a signal pad; and the second pad is a ground pad.

19 . The circuit of claim 17 , wherein:
the first pad is a first supply voltage pad; and the second pad is a ground pad.

20 . The circuit of claim 15 , further comprising a second electrostatic discharge protection device, wherein:
the second electrostatic discharge protection device has a substantially identical structure as the first electrostatic discharge protection device; and the second electrostatic discharge protection device and the first electrostatic discharge protection device are connected in series between the I/O terminal and ground.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Yi-Feng
• Lee Jam-Wem

Classifications

• H10D89/611

  using diodes as protective elements · CPC title

• H10D84/619

  Combinations of lateral BJTs and one or more of diodes, resistors or capacitors · CPC title

• H10D84/121

  BJTs having built-in components · CPC title

• H10D62/184

  of lateral BJTs · CPC title

• H10D62/137

  Collector regions of BJTs · CPC title