Thermally enhanced package-on-package structure

Patent metadata

Field	Value
Publication number	US-2016276308-A1
Application number	US-201514806604-A
Country	US
Kind code	A1
Filing date	Jul 22, 2015
Priority date	Mar 17, 2015
Publication date	Sep 22, 2016
Grant date	—

Abstract

A semiconductor package comprises a bottom package and a top package. The bottom package comprises at least one bottom-package semiconductor device. The top package is on the bottom package and comprises a first side, a second side, a package substrate, a plurality of top-package semiconductor devices, and at least one thermal path. The package substrate is disposed at the first side of the top package. The plurality of top-package semiconductor devices is disposed on the package substrate. The at least one thermal path is disposed between a first top-package semiconductor device and a second top-package semiconductor device, and the thermal path extends from the first side of the top package through the package substrate to the second side of the top package.

First claim

1 . A package-on-package (POP) structure, comprising:
a top package comprising:
a package substrate comprising a first side and a second side;
a plurality of top-package semiconductor devices on the first side of the package substrate;
a molding material layer formed on and between the plurality of top-package semiconductor devices; and
a thermal path disposed between a first top-package semiconductor device and a second top-package semiconductor device, the thermal path extending through the package substrate from the second side of the package substrate to a top surface of the molding material layer.

2 . The POP structure according to claim 1 , further comprising a bottom package comprising at least one bottom-package semiconductor device, and
wherein the at least one thermal path is disposed over and is thermally coupled to the at least one bottom-package semiconductor device.

3 . The POP structure according to claim 2 , wherein the at least one thermal path is disposed substantially centered over the at one bottom-package semiconductor device.

4 . The POP structure according to claim 2 , wherein the at least one bottom-package semiconductor device comprises a backside metallization that is thermally coupled to the at least one thermal path.

5 . The POP structure according to claim 2 , wherein the top package further comprises:
a thermal interface material (TIM) layer formed on a top surface of the molding material layer; and a heat slug formed on a top surface of the TIM layer.

6 . The POP structure according to claim 2 , wherein the at least one thermal path comprises at least one via extending through the top package from the second side of the package substrate to the top surface of the molding material layer, the at least one via being filled with a low thermal resistance material.

7 . The POP structure according to claim 2 , wherein the package substrate comprises at least one via extending through the package substrate and in alignment with the at least one thermal path, the at least one via extending through the package substrate being filled with a low thermal resistance material, and
wherein the at least one thermal path comprises at least one trench extending through the top package from the first side of the package substrate to the top surface of the molding material layer in alignment with the at least one via extending through the package substrate, the at least one trench being filled with a low thermal resistance material.

8 . The POP structure according to claim 7 , wherein the at least one trench is further filled with a heat slug and the low thermal resistance material.

9 . A semiconductor package, comprising:
a bottom package comprising at least one bottom-package semiconductor device; and a top package on the bottom package, the top package comprising a first side and a second side, a package substrate disposed at the first side of the top package, a plurality of top-package semiconductor devices disposed on the package substrate, and at least one thermal path disposed between a first top-package semiconductor device and a second top-package semiconductor device, the thermal path extending from the first side of the top package through the package substrate to the second side of the top package.

10 . The semiconductor device according to claim 9 , wherein the at least one thermal path is disposed over and is thermally coupled to the at least one bottom-package semiconductor device.

11 . The semiconductor device according to claim 10 , wherein the at least one thermal path is disposed substantially centered over the at one bottom-package semiconductor device.

12 . The semiconductor device according to claim 10 , wherein the at least one bottom-package semiconductor device comprises a backside metallization that is thermally coupled to the at least one thermal path.

13 . The semiconductor device according to claim 10 , wherein the top package further comprises a molding material layer formed on and between the plurality of top-package semiconductor devices, and
wherein the at least one thermal path extends through the molding material layer between the first top-package semiconductor device and the second top-package semiconductor device from the first side to the second side of the top package.

14 . The semiconductor device according to claim 13 , wherein the top package further comprises:
a thermal interface material (TIM) layer formed on a top surface of the molding material layer; and a heat slug formed on a top surface of the TIM layer.

15 . The semiconductor device according to claim 13 , wherein the at least one thermal path comprises at least one via extending through the top package from the first side to the top surface of the molding material layer, the at least one via being filled with a low thermal resistance material.

16 . The semiconductor device according to claim 13 , wherein the package substrate of the bottom package comprises at least one via extending through the package substrate and in alignment with the at least one thermal path, the at least one via extending through the package substrate being filled with a low thermal resistance material, and
wherein the at least one thermal path comprises at least one trench extending through the top package from the first side of the package substrate to the top surface of the molding material layer in alignment with the at least one via extending through the package substrate, the at least one trench being filled with a low thermal resistance material.

17 . The semiconductor device according to claim 16 , wherein the at least one trench is further filled with a heat slug and the low thermal resistance material.

18 . A semiconductor package, comprising:
a bottom package comprising:
a bottom-package substrate comprising a first side and a second side; and
at least one controller-type semiconductor device on the first side of the bottom-package substrate, the at least one controller-type semiconductor device comprising a first side, a second side and a backside metallization on the first side of the controller-type semiconductor device; and
a top package on the bottom package, the top package comprising:
a first side and a second side;
a package substrate disposed at the first side of the top package;
a plurality of top-package semiconductor devices on the package substrate, at least one top-package semiconductor device comprising a memory semiconductor device;
a molding material layer formed on and between the plurality of top-package semiconductor devices;
a thermal interface material (TIM) layer formed on a top surface of the molding material layer; and
a heat slug formed on a top surface of the TIM layer and being thermally coupled to the TIM layer; and
at least one thermal path disposed between a first top-package semiconductor device and a second top-package semiconductor device, the thermal path extending from the first side of the top package through the package substrate to the TIM layer, and the thermal path being disposed over and being thermally coupled to the at least one bottom-package semiconductor device.

19 . The semiconductor device according to claim 18 , wherein the at least one thermal path comprises at least one via extending through the top package from the first side to the top surface of the molding material layer, the at least one via being filled with a low thermal resistance material.

20 . The semiconductor device according to claim 18 , wherein th

Assignees

• Samsung Electronics Co Ltd

Inventors

• Min Sunghwan
• Jung Yoonha
• Choi Jungyong
• Kim Sung Hoon

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title