Semiconductor device

Patent metadata

Field	Value
Publication number	US-2016276261-A1
Application number	US-201514789505-A
Country	US
Kind code	A1
Filing date	Jul 1, 2015
Priority date	Mar 20, 2015
Publication date	Sep 22, 2016
Grant date	—

Abstract

A semiconductor device includes a first memory block and a second memory block in a cell region and a first transistor and a second transistor, respectively corresponding to the first and second memory blocks, in a pass transistor region located below the cell region, wherein each of the first and second transistors includes: a first gate electrode coupled to the first memory block and a second gate electrode coupled to the second memory block.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first memory block and a second memory block in a cell region; and a first transistor and a second transistor, respectively corresponding to the first and second memory blocks, in a pass transistor region located below the cell region, wherein each of the first and second transistors includes:
a first gate electrode coupled to the first memory block; and
a second gate electrode coupled to the second memory block.

2 . The semiconductor device according to claim 1 , wherein each of the first and second transistors further includes:
an active region, wherein the first gate electrode and the second gate electrode are arranged over and cross the active region.

3 . The semiconductor device according to claim 2 , wherein each of the first memory block and the second memory block includes:
a word line multilayered structure that extends in parallel to a long axis of the active region.

4 . The semiconductor device according to claim 3 , further comprising:
a plurality of transistors, as the first or second transistor, arranged along the long axis of the active region direction of the first memory block and the second memory block.

5 . The semiconductor device according to claim 1 , wherein the first memory block and the second memory block are separated from each other by a slit.

6 . The semiconductor device according to claim 1 , wherein each of the first memory block and the second memory block includes:
a pad structure having a step-shaped word line multilayered structure.

7 . The semiconductor device according to claim 6 , wherein the first gate electrode and the second gate electrode are coupled to respective pad structures contained in the first memory block and the second memory block.

8 . The semiconductor device according to claim 2 , wherein the first gate electrode is coupled to the first memory block through a first local line contact plug.

9 . The semiconductor device according to claim 8 , wherein the first local line contact plug is formed over the active region at one side of the first gate electrode.

10 . The semiconductor device according to claim 2 , wherein the second gate electrode is coupled to the second memory block through a second local line contact plug.

11 . The semiconductor device according to claim 10 , wherein the second local line contact plug is formed over the active region at one side of the second gate electrode.

12 . The semiconductor device according to claim 2 , further comprising:
a global line contact plug coupled to the active region between the first gate electrode and the second gate electrode; and a global word line coupled to the global contact plug.

13 . A semiconductor device comprising:
a cell region configured to include a first memory block and a second memory block; and a pass transistor region located below the cell region, wherein the pass transistor region includes: a first transistor located below the first memory block, and includes a first gate electrode coupled to the first memory block and a second gate electrode coupled to the second memory block; and a second transistor located below the second memory block, and includes a third gate electrode coupled to the first memory block and a fourth gate electrode coupled to the second memory block.

14 . The semiconductor device according to claim 13 , wherein the pass transistor region includes a first active region and a second active region, the first gate electrode and the second gate electrode are formed over a first active region, and the third gate electrode and the fourth gate electrode are formed over a second active region.

15 . The semiconductor device according to claim 14 , wherein each of the first memory block and the second memory block includes a word line multilayered structure extended along a direction parallel to long axes of the first active region and the second active region.

16 . The semiconductor device according to claim 13 , wherein the first memory block and the second memory block are separated from each other by a slit, and each of the first memory block and the second memory block further includes a pad structure having a step-shaped word line multilayered structure.

17 . The semiconductor device according to claim 14 , wherein the first gate electrode and the third gate electrode are coupled to a pad structure contained in the first memory block through a first local contact plug.

18 . The semiconductor device according to claim 17 , wherein the first local contact plug is located not only over the first active region arranged at one side of the first gate electrode, but also over the second active region arranged at one side of the third gate electrode.

19 . The semiconductor device according to claim 14 , wherein the second gate electrode and the fourth gate electrode are coupled to a pad structure contained in the second memory block through a second local contact plug.

20 . The semiconductor device according to claim 19 , wherein the second local contact plug is located not only over the first active region arranged at one side of the second gate electrode, but also over the second active region arranged at one side of the fourth gate electrode.

21 . The semiconductor device according to claim 14 , further comprising:
a global contact plug coupled not only to the first active region disposed between the first gate electrode and the second gate electrode, but also to the second active region disposed between the third gate electrode and the fourth gate electrode; and a global word line coupled to the global contact plug.

Assignees

• Sk Hynix Inc

Inventors

• Oh Sung Lae
• Eom Dae Sung

Classifications

• H01L27/1052

  Electricity · mapped topic

• H01L27/0688

  Electricity · mapped topic

• H01L27/088

  Electricity · mapped topic

• H01L23/528 Primary

  Electricity · mapped topic

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title