Semiconductor Device and Method to Minimize Stress on Stack Via

Patent metadata

Field	Value
Publication number	US-2016276237-A1
Application number	US-201615169095-A
Country	US
Kind code	A1
Filing date	May 31, 2016
Priority date	Jun 16, 2014
Publication date	Sep 22, 2016
Grant date	—

Abstract

A semiconductor device has a semiconductor die. A first insulating layer is disposed over the semiconductor die. A first via is formed in the first insulating layer over a contact pad of the semiconductor die. A first conductive layer is disposed over the first insulating layer and in the first via. A second insulating layer is disposed over a portion of the first insulating layer and first conductive layer. An island of the second insulating layer is formed over the first conductive layer and within the first via. The first conductive layer adjacent to the island is devoid of the second insulating layer. A second conductive layer is disposed over the first conductive layer, second insulating layer, and island. The second conductive layer has a corrugated structure. A width of the island is greater than a width of the first via.

First claim

What is claimed:

1 . A method of making a semiconductor device, comprising:
providing a semiconductor die; disposing a first insulating layer over the semiconductor die; forming a first via in the first insulating layer over a contact pad of the semiconductor die; disposing a first conductive layer over the first insulating layer and in the first via; disposing a second insulating layer over the first insulating layer and first conductive layer; and removing a portion of the second insulating layer to form an island of the second insulating layer over the first conductive layer and within the first via.

2 . The method of claim 1 , further including disposing a second conductive layer over the first conductive layer, second insulating layer, and island.

3 . The method of claim 2 , wherein the second conductive layer has a corrugated structure.

4 . The method of claim 2 , further including disposing a bump over the second conductive layer and the island.

5 . The method of claim 1 , wherein a width of the island is greater than a width of the first via.

6 . The method of claim 1 , wherein the island reduces von Mises stress on a portion of the first conductive layer disposed in the first via.

7 . The method of claim 1 , wherein the second insulating layer is a compliant dielectric material.

8 . A method of making a semiconductor device, comprising:
providing a semiconductor die; disposing a first insulating layer over the semiconductor die; forming a first via in the first insulating layer over a contact pad of the semiconductor die; disposing a first conductive layer over the first insulating layer and in the first via; disposing a second insulating layer over the first insulating layer and first conductive layer; forming a second via in the second insulating layer over the first conductive layer and the first via; disposing a second conductive layer over the first conductive layer and second conductive layer; and forming a third via in the second conductive layer and aligned with the first via.

9 . The method of claim 8 , wherein the second conductive layer has a ring or donut shape.

10 . The method of claim 8 , wherein the third via is off-center with respect to the second conductive layer.

11 . The method of claim 8 , further including disposing a bump over the second conductive layer and the first conductive layer.

12 . The method of claim 11 , wherein the bump contacts the first conductive layer.

13 . The method of claim 8 , wherein a width of the third via is greater than a width of the first via.

14 . A semiconductor device, comprising:
a semiconductor die; a first insulating layer disposed over the semiconductor die; a first via formed in the first insulating layer over a contact pad of the semiconductor die; a first conductive layer disposed over the first insulating layer and in the first via; a second insulating layer disposed over a portion of the first insulating layer and first conductive layer; and an island of the second insulating layer formed over the first conductive layer and within the first via wherein the first conductive layer adjacent to the island is devoid of the second insulating layer.

15 . The semiconductor device of claim 14 , further including a second conductive layer disposed over the first conductive layer, second insulating layer, and island.

16 . The semiconductor device of claim 15 , wherein the second conductive layer has a corrugated structure.

17 . The semiconductor device of claim 15 , further including a bump disposed over the second conductive layer and the island.

18 . The semiconductor device of claim 14 , wherein a width of the island is greater than a width of the first via.

19 . The semiconductor device of claim 14 , wherein the island reduces von Mises stress on a portion of the first conductive layer disposed in the first via.

20 . A semiconductor device, comprising:
a semiconductor die; a first insulating layer disposed over the semiconductor die; a first via formed in the first insulating layer over a contact pad of the semiconductor die; a first conductive layer disposed over the first insulating layer and in the first via; a second insulating layer disposed over the first insulating layer and first conductive layer; a second via formed in the second insulating layer over the first conductive layer and the first via; a second conductive layer disposed over the first conductive layer and second conductive layer; and a third via formed in the second conductive layer and aligned with the first via.

21 . The semiconductor device of claim 20 , wherein the second conductive layer has a ring or donut shape.

22 . The semiconductor device of claim 20 , wherein the third via is off-center with respect to the second conductive layer.

23 . The semiconductor device of claim 20 , further including a bump disposed over the second conductive layer and the first conductive layer.

24 . The semiconductor device of claim 23 , wherein the bump contacts the first conductive layer.

25 . The semiconductor device of claim 20 , wherein a width of the third via is greater than a width of the first via.

Assignees

• Stats Chippac Pte Ltd

Inventors

• Lin Yaojian
• Chow Seng Guan

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/40

  characterised by their materials · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title