Coordinating joint operation of multiple hypervisors in a computer system

Patent metadata

Field	Value
Publication number	US-2016274931-A1
Application number	US-201615062861-A
Country	US
Kind code	A1
Filing date	Mar 7, 2016
Priority date	Mar 16, 2015
Publication date	Sep 22, 2016
Grant date	—

Abstract

In a computer system, joint operation of multiple hypervisors is coordinated. A persistent hypervisor and a non-persistent hypervisor are executed. The non-persistent hypervisor is executed in the supervisor mode according to an operating regime controlled by a scheduler engine, and the persistent hypervisor is executed in the hypervisor mode under the control of a handler engine. The handler engine monitors, and responds, to an attempted mode transition of the processor between the hypervisor and supervisor modes, and coordinates the suspension and resumption, as appropriate, of the persistent hypervisor.

First claim

1 . A system for coordinating joint operation of multiple hypervisors, the system comprising:
a computing platform having a processor, data storage, and input/output facilities, the processor being switchable between a hypervisor mode and a supervisor mode, the hypervisor mode providing a higher privilege level than the supervisor mode, the computing platform containing instructions that, when executed by the computing platform, cause the computing platform to implement: a persistent hypervisor and a non-persistent hypervisor; a scheduler engine configured to coordinate operation of the non-persistent hypervisor in the supervisor mode; a handler engine configured to coordinate operation of the persistent hypervisor in the hypervisor mode such that:
the handler engine monitors, and responds, to an attempted mode transition of the processor between the hypervisor and supervisor modes;
in response to an attempted mode transition from the hypervisor mode to the supervisor mode, the handler engine suspends execution of the persistent hypervisor, including saving of a state of the processor, and transitions the processor to execute the non-persistent hypervisor in the supervisor mode, wherein the handler engine is configured to monitor at least one command associated with a processor mode transition between the hypervisor mode and the supervisor mode; and
wherein in response to a conclusion of execution of supervisor-mode instruction, the handler engine suspends execution of the non-persistent hypervisor, including saving of the processor state, and transitions the processor to execute the persistent hypervisor in the hypervisor mode.

2 . The system of claim 1 , wherein the handler engine is realized using an operating system driver.

3 . The system of claim 1 , wherein the handler engine is configured to monitor status information of the computing platform indicative of a processor mode transition between the hypervisor mode and the supervisor mode.

4 . (canceled)

5 . The system of claim 4 , wherein the at least one command includes a vmrun command.

6 . The system of claim 1 , wherein the handler engine is configured to detect at least one parameter state change associated with a processor mode transition between the hypervisor mode and the supervisor mode.

7 . The system of claim 6 , wherein the parameter state change includes re-loading of a pages directory.

8 . The system of claim 6 , wherein the parameter state change includes re-loading of a CR3 registry.

9 . The system of claim 1 , wherein the handler engine includes an interceptor engine configured to suspend execution of a processor mode change, in response to a detection of an attempt to made such a mode change, until a series of actions for controlling operation of the persistent hypervisor is completed.

10 . The system of claim 1 , wherein the handler engine is configured such that, in response to an attempted mode transition from the hypervisor mode to the supervisor mode, the handler engine determines a processor mode in which the mode transition was originated and, based on the determination of that processor mode, suspension of the persistent hypervisor is either permitted, or not permitted.

11 . The system of claim 1 , wherein the handler engine is configured to monitor the scheduler engine for a condition indicating a call to stop execution of a non-persistent hypervisor and, in response to the condition, the handler engine resumes operation of a suspended persistent hypervisor.

12 . A method for coordinating joint operation of multiple hypervisors in a computing system having a processor that is switchable between a hypervisor mode and a supervisor mode, the hypervisor mode providing a higher privilege level than the supervisor mode, the method comprising:
executing, by the computing system, a persistent hypervisor and a non-persistent hypervisor, the non-persistent hypervisor being executed in the supervisor mode according to an operating regime controlled by a scheduler engine; executing, by the computing system, a handler engine to coordinate operation of the persistent hypervisor in the hypervisor mode such that:
the handler engine monitors, and responds, to an attempted mode transition of the processor between the hypervisor and supervisor modes;
in response to an attempted mode transition from the hypervisor mode to the supervisor mode, the handler engine suspends execution of the persistent hypervisor, including saving of a state of the processor, and transitions the processor to execute the non-persistent hypervisor in the supervisor mode, wherein the handler engine detects at least one parameter state change associated with a processor mode transition between the hypervisor mode and the supervisor mode; and
wherein in response to a conclusion of execution of supervisor-mode instruction, the handler engine suspends execution of the non-persistent hypervisor, including saving of the processor state, and transitions the processor to execute the persistent hypervisor in the hypervisor mode.

13 . The method of claim 12 , wherein the handler engine monitors status information of the computing platform indicative of a processor mode transition between the hypervisor mode and the supervisor mode.

14 . The method of claim 12 , wherein the handler engine monitors at least one command associated with a processor mode transition between the hypervisor mode and the supervisor mode.

15 . The method of claim 14 , wherein the at least one command includes a vmrun command.

16 . (canceled)

17 . The method of claim 16 , wherein the parameter state change includes re-loading of a pages directory or of a CR3 registry.

18 . The method of claim 12 , wherein the handler engine suspends execution of a processor mode change, in response to a detection of an attempt to made such a mode change, until a series of actions for controlling operation of the persistent hypervisor is completed.

19 . The method of claim 12 , wherein in response to an attempted mode transition from the hypervisor mode to the supervisor mode, the handler engine determines a processor mode in which the mode transition was originated and, based on the determination of that processor mode, suspension of the persistent hypervisor is either permitted, or not permitted.

20 . The method of claim 12 , wherein the handler engine monitors the scheduler engine for a condition indicating a call to stop execution of a non-persistent hypervisor and, in response to the condition, the handler engine resumes operation of a suspended persistent hypervisor.

21 . A system for coordinating joint operation of multiple hypervisors in a computing system having a processor that is switchable between a hypervisor mode and a supervisor mode, the hypervisor mode providing a higher privilege level than the supervisor mode, the system comprising:
means for executing a persistent hypervisor and a non-persistent hypervisor, the non-persistent hypervisor being executed in the supervisor mode according to an operating regime controlled by a scheduler engine; means for executing a handler engine to coordinate operation of the persistent hypervisor in the hypervisor mode such that:
the handler engine monitors, and responds, to an attempted mode transition of the processor between the hypervisor and supervisor modes;
in response to an attempted mode transition from the hypervisor mode to the supervisor mode, the handler engine suspends execution of the persistent hypervisor, including sa

Assignees

• Kaspersky Lab Zao

Inventors

• Levchenko Vyacheslav I
• Kumagin Igor Y

Classifications

• G06F2009/45587

  Isolation or security of virtual machine instances · CPC title

• G06F2009/45575

  Starting, stopping, suspending or resuming virtual machine instances · CPC title

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title

• G06F2009/45562

  Creating, deleting, cloning virtual machine instances · CPC title