Apparatus for Improving Signal-to-Noise Performance of Projected Capacitance Touch Screens and Panels

Patent metadata

Field	Value
Publication number	US-2016274731-A1
Application number	US-201615168319-A
Country	US
Kind code	A1
Filing date	May 31, 2016
Priority date	Apr 16, 2014
Publication date	Sep 22, 2016
Grant date	—

Abstract

Improved signal-to-noise performance of projected capacitance touch screens and panels is provided by an integrated circuit regulated high voltage source and high voltage/current drivers coupled to a plurality of projected capacitive touch elements that are controlled by a microcontroller. The single integrated circuit high voltage generator/driver may comprise a voltage boost circuit, a voltage reference, power-on-reset (POR), soft start, a plurality of voltage level shifters and a serial interface for coupling to the microcontroller that may control all functions related to using the projected capacitance touch screens and panels.

First claim

1 - 13 . (canceled)

14 . A system for determining locations of touches detecting touches on a projected capacitance touch sensing surface, said system comprising:
a first plurality of electrodes arranged in a parallel orientation having a first axis, wherein each of the first plurality of electrodes comprises a self capacitance; a second plurality of electrodes arranged in a parallel orientation having a second axis substantially perpendicular to the first axis, the first plurality of electrodes are located over the second plurality of electrodes and form a plurality of nodes comprising overlapping intersections of the first and second plurality of electrodes, wherein each of the plurality of nodes comprises a mutual capacitance; a high voltage generator/driver comprising a voltage boost circuit having a high voltage output, a voltage reference coupled to the voltage boost circuit, a plurality of voltage level shifters/drivers, each one having a high voltage input coupled to the high voltage output of the voltage boost circuit and an independently controllable high voltage output coupled to a respective one of the first and second plurality of electrodes, logic circuits coupled to the plurality of voltage level shifters/drivers, wherein the logic circuits control the high voltage outputs thereof, and a serial-to-parallel interface coupled to the logic circuits and the voltage boost circuit; a mixed signal device comprising a capacitive touch analog front end having a plurality of analog inputs coupled to respective ones of the first and second plurality of electrodes, an analog-to-digital converter (ADC) coupled to the capacitive touch front end, a digital processor and memory, wherein at least one output from the ADC is coupled to the digital processor; and a serial interface coupled to the digital processor and the serial-to-parallel interface of the high voltage generator/driver; wherein values of the self capacitances are measured using the high voltage for each of the first plurality of electrodes by the analog front end, the values of the measured self capacitances are stored in the memory, values of the mutual capacitances of the nodes of at least one of the first electrodes having at least one of the largest values of self capacitance are measured using the high voltage by the analog front end, the values of the measured mutual capacitances are stored in the memory and the digital processor uses the stored self and mutual capacitance values for determining locations of the touches and the respective forces applied to the touch sensing surface.

15 . The system as recited in claim 14 , wherein the mixed signal device is a mixed signal microcontroller integrated circuit.

16 . The system as recited in claim 14 , wherein the high voltage generator/driver comprises an integrated circuit.

17 . The system as recited in claim 14 , wherein the high voltage is greater than a supply voltage powering the high voltage generator/driver and the mixed signal device.

18 . A method for improving signal-to-noise performance of a projected capacitance touch sensing surface, said method comprising the steps of:
providing a first plurality of electrodes arranged in a parallel orientation having a first axis, wherein each of the first plurality of electrodes comprises a self capacitance; providing a second plurality of electrodes arranged in a parallel orientation having a second axis substantially perpendicular to the first axis, the first plurality of electrodes are located over the second plurality of electrodes and form a plurality of nodes comprising overlapping intersections of the first and second plurality of electrodes, wherein each of the plurality of nodes comprises a mutual capacitance; charging the first plurality of electrodes to a voltage greater than a power source voltage; discharging the second plurality of electrodes to a power source common; scanning the first plurality of electrodes for determining values of the self capacitances thereof; comparing the values of the scanned self capacitances to determine which one of the first plurality of electrodes has the largest value of self capacitance; scanning the nodes of the one of the first plurality of electrodes having the largest value of self capacitance for determining values of the mutual capacitances of the respective plurality of nodes; comparing the values of the scanned mutual capacitances of the respective plurality of nodes on the first electrode having the largest value of self capacitance, wherein the node having the largest value of mutual capacitance is a location of a touch on the touch sensing surface.

19 . The method as recited in claim 18 , wherein the self and mutual capacitance values are measured with an analog front end and an analog-to-digital converter (ADC).

20 . The method as recited in claim 19 , wherein the self and mutual capacitance values are stored in a memory of a digital processor.

21 . The method as recited in claim 19 , wherein the self and mutual capacitance values are determined by a capacitive voltage divider method.

22 . The method as recited in claim 19 , wherein the self and mutual capacitance values are determined with a charge time measurement unit.

23 . The method according to claim 18 , wherein the voltage greater than a power source voltage is generated by:
coupling a voltage reference to a voltage boost circuit; generating a high voltage by the voltage boost circuit; coupling high voltage inputs of a plurality of voltage level shifters/drivers to a high voltage output of the voltage boost circuit, wherein the plurality of voltage level shifters/drivers each comprise an independently controllable high voltage output; coupling logic circuits to the plurality of voltage level shifters/drivers, wherein the logic circuits control the high voltage outputs thereof.

24 . The method as recited in claim 23 , further comprising:
providing a serial-to-parallel interface coupled to the logic circuits and the voltage boost circuit, and coupling a power-on-reset (POR) circuit to the voltage boost circuit and the serial-to-parallel interface.

25 . The method as recited in claim 23 , wherein the logic circuits are a plurality of AND gates, the method further comprising: coupling an output enable control to an input of each one of the plurality of AND gates.

26 . The method as recited in claim 23 , further comprising: coupling a high voltage output capacitor between the output of the voltage boost circuit and a power source common.

27 . The method as recited in claim 23 , further comprising: coupling a boost inductor between a power input to the voltage boost circuit and a power source.

28 . The method as recited in claim 23 , wherein the outputs of the plurality of voltage level shifters/drivers are tri-state and having selectable output states at a power source common, the high voltage output or a high off resistance.

29 . The method as recited in claim 24 , wherein the serial-to-parallel interface further comprises configuration and data storage registers, the method further comprising: storing parameters of the voltage boost circuit and output states of the plurality of voltage level shifters/drivers in the configuration and data storage register.

30 . The method as recited in claim 23 , further comprising: disabling during a soft start the outputs of the plurality of voltage level shifters/drivers.

31 . The method as recited in claim 23 , wherein the logic circuits and input circuits of the plurality

Assignees

• Microchip Tech Inc

Inventors

• Sharma Attma
• Walton Cory
• Hanauer Jerry

Classifications

• H03K17/22

  Modifications for ensuring a predetermined initial state when the supply voltage has been applied (bi-stable generators H03K3/12) · CPC title

• H03K19/017509

  Interface arrangements · CPC title

• G06F2203/04106

  Multi-sensing digitiser, i.e. digitiser using at least two different sensing technologies simultaneously or alternatively, e.g. for detecting pen and finger, for saving power or for improving position detection · CPC title

• G06F3/044

  by capacitive means · CPC title

• G06F3/0418 Primary

  for error correction or compensation, e.g. based on parallax, calibration or alignment · CPC title