Method of enabling sleep mode, memory control circuit unit and storage apparatus

Patent metadata

Field	Value
Publication number	US-2016274648-A1
Application number	US-201514698870-A
Country	US
Kind code	A1
Filing date	Apr 29, 2015
Priority date	Mar 19, 2015
Publication date	Sep 22, 2016
Grant date	—

Abstract

A sleep mode enabling method for a memory storage apparatus is provided. The method includes: setting a sleep pin connecting flag as a first value if a potential signal on a device sleep signal pin is at a second logic level opposite to an initial first logic level; setting a device sleep function flag as the first value in response to a device sleep function enabling command received from a host system; and enabling a device sleep function of the memory storage apparatus if the device sleep function enabling command is received and the device sleep function flag is set as the first value.

First claim

What is claimed is:

1 . A sleep mode enabling method for a memory storage apparatus, wherein a potential signal on a device sleep signal pin of the memory storage apparatus is initially at a first logic level, the sleep mode enabling method comprising:
setting a sleep pin connecting flag as a first value if the potential signal on the device sleep signal pin of the memory storage apparatus is at a second logic level opposite to the first logic level; and enabling a device sleep function of the memory storage apparatus if a device sleep function enabling command is received and the sleep pin connecting flag is set as the first value.

2 . The sleep mode enabling method of claim 1 , further comprising: setting a device sleep function flag as the first value in response to the device sleep function enabling command received from a host system.

3 . The sleep mode enabling method of claim 2 , wherein the step of enabling the device sleep function of the memory storage apparatus if the device sleep function enabling command is received and the sleep pin connecting flag is set as the first value comprises:
enabling the device sleep function of the memory storage apparatus if the device sleep function enabling command is received when the sleep pin connecting flag is set as the first value and the device sleep function flag is set as the first value.

4 . The sleep mode enabling method of claim 1 , further comprising:
enabling the memory storage apparatus to enter a sleep mode when the device sleep function of the memory storage apparatus is enabled and the potential signal on the device sleep signal pin of the memory storage apparatus at the first logic level is detected.

5 . The sleep mode enabling method of claim 3 , wherein the step of enabling the device sleep function of the memory storage apparatus when the sleep pin connecting flag is set as the first value and the device sleep function flag is set as the first value comprises:
determining whether the sleep pin connecting flag is set as first value after setting the device sleep function flag as the first value; and enabling the device sleep function of the memory storage apparatus if the sleep pin connecting flag is set as the first value.

6 . The sleep mode enabling method of claim 3 , wherein the step of enabling the device sleep function of the memory storage apparatus when the sleep pin connecting flag is set as the first value and the device sleep function flag is set as the first value comprises:
determining whether the device sleep function flag is set as the first value after setting the sleep pin connecting flag as the first value; and enabling the device sleep function of the memory storage apparatus if the device sleep function flag is set as the first value.

7 . The sleep mode enabling method of claim 1 , wherein the first logic level is a high logic level and the second logic level is a low logic level.

8 . The sleep mode enabling method of claim 4 , further comprising:
detecting whether the potential signal on the device sleep signal pin of the memory storage apparatus changes from the first logic level to the second logic level after the memory storage apparatus enters the sleep mode; and restoring the memory storage apparatus from the sleep mode to an operation mode if detecting that the potential signal on the device sleep signal pin of the memory storage apparatus changes from the first logic level to the second logic level.

9 . The sleep mode enabling method of claim 4 , wherein the step of enabling the memory storage apparatus to enter the sleep mode when the device sleep function of the memory storage apparatus is enabled and the potential signal on the device sleep signal pin of the memory storage apparatus at the first logic level is detected comprises:
determining whether the potential signal on the device sleep signal pin of the memory storage apparatus is at the first logic level after enabling the device sleep function of the memory storage apparatus; and enabling the memory storage apparatus to enter the sleep mode if the potential signal on the device sleep signal pin of the memory storage apparatus is at the first logic level.

10 . A memory control circuit unit for controlling a memory storage apparatus, wherein a potential signal on a device sleep signal pin of the memory storage apparatus is initially at a first logic level, the memory control circuit unit comprising:
a host interface configured to electrically connect to a host system; a memory interface configured to couple to a rewritable non-volatile memory module; a buffer storage unit configured to record a sleep pin connecting flag; and a memory management circuit coupled to the memory interface, the host interface and the buffer storage unit, wherein the memory management circuit is configured to set the sleep pin connecting flag as a first value if the potential signal on the device sleep signal pin of the memory storage apparatus is at a second logic level opposite to the first logic level, wherein the memory management circuit is further configured to enable a device sleep function if a device sleep function enabling command is received and the sleep pin connecting flag is set as the first value.

11 . The memory control circuit unit of claim 10 , wherein the memory management circuit is further configured to set a device sleep function flag as the first value in response to the device sleep function enabling command received from the host system through the host interface,
wherein the buffer storage unit records the device sleep function flag.

12 . The memory control circuit unit of claim 11 ,
wherein in the operation of enabling the device sleep function if the device sleep function enabling command is received and the sleep pin connecting flag is set as the first value, the memory management circuit enables the device sleep function if the device sleep function enabling command is received when the sleep pin connecting flag is set as the first value and the device sleep function flag is set as the first value.

13 . The memory control circuit unit of claim 10 ,
wherein the memory management circuit is further configured to enter a sleep mode when the device sleep function is enabled and the potential signal on the device sleep signal pin of the memory storage apparatus at the first logic level is detected.

14 . The memory control circuit unit of claim 12 , wherein in the operation of enabling the device sleep function when the sleep pin connecting flag is set as the first value and the device sleep function flag is set as the first value, the memory management circuit determines whether the sleep pin connecting flag is set as first value after setting the device sleep function flag as the first value,
wherein the memory management circuit enables the device sleep function if the sleep pin connecting flag is set as the first value.

15 . The memory control circuit unit of claim 12 , wherein in the operation of enabling the device sleep function when the sleep pin connecting flag is set as the first value and the device sleep function flag is set as the first value, the memory management circuit determines whether the device sleep function flag is set as the first value after setting the sleep pin connecting flag as the first value,
wherein the memory management circuit enables the device sleep function if the device sleep function flag is set as the first value.

16 . The memory control circuit unit of claim 10 , wherein the first logic level is a high logic level and the second logic level is a

Assignees

• Phison Electronics Corp

Inventors

• Chu Chien-Hua

Classifications

• G06F1/3225

  of memory devices · CPC title

• G06F1/3221

  of disk drive devices · CPC title

• G06F1/3268 Primary

  Power saving in hard disk drive · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title