Thin Form Factor Computational Array Cameras and Modular Array Cameras

Patent metadata

Field	Value
Publication number	US-2016269651-A1
Application number	US-201615012044-A
Country	US
Kind code	A1
Filing date	Feb 1, 2016
Priority date	Feb 24, 2013
Publication date	Sep 15, 2016
Grant date	—

Abstract

Systems and methods in accordance with embodiments of the invention implement modular array cameras using sub-array modules. In one embodiment, an X×Y sub-array module includes: an X×Y arrangement of focal planes, where X and Y are each greater than or equal to 1; and an X×Y arrangement of lens stacks, the X×Y arrangement of lens stacks being disposed relative to the X×Y arrangement of focal planes so as to form an X×Y arrangement of cameras, where each lens stack has a field of view that is shifted with respect to the field-of-views of each other lens stack so that each shift includes a sub-pixel shifted view of the scene; and image data output circuitry that is configured to output image data from the X×Y sub-array module that can be aggregated with image data from other sub-array modules so that an image of the scene can be constructed.

First claim

What is claimed is:

1 . An X×Y sub-array module comprising:
an X×Y arrangement of focal planes, wherein:
X and Y are each greater than or equal to 1;
each focal plane comprises a plurality of rows of pixels that also form a plurality of columns of pixels; and
each focal plane does not include pixels from another focal plane; and

an X×Y arrangement of lens stacks, the X×Y arrangement of lens stacks being disposed relative to the X×Y arrangement of focal planes so as to form an X×Y arrangement of cameras, each of which being configured to independently capture an image of a scene, wherein each lens stack has a field of view that is shifted with respect to the field-of-views of each other lens stack so that each shift includes a sub-pixel shifted view of the scene; and
image data output circuitry that is configured to output image data from the X×Y sub-array module that can be aggregated with image data from other sub-array modules so that an image of the scene can be constructed.

2 . The X×Y sub-array module of claim 1 , wherein X is 1.

3 . The X×Y sub-array module of claim 1 , wherein X and Y are each greater than 1.

4 . The X×Y sub-array module of claim 1 , wherein the arrangement of cameras are embodied within a single monolithic structure

5 . An M×N array camera comprising:
a plurality of X×Y sub-array modules, each comprising:
an X×Y arrangement of focal planes, wherein:
X and Y are each greater than or equal to 1;
each focal plane comprises a plurality of rows of pixels that also form a plurality of columns of pixels; and
each focal plane does not include pixels from another focal plane; and

an X×Y arrangement of lens stacks, the X×Y arrangement of lens stacks being disposed relative to the X×Y arrangement of focal planes so as to form an X×Y arrangement of cameras, each of which being configured to independently capture an image of a scene, wherein each lens stack has a field of view that is shifted with respect to the field-of-views of each other lens stack so that each shift includes a sub-pixel shifted view of the scene; and
image data output circuitry that is configured to output image data from the sub-array module that can be aggregated with image data from other sub-array modules so that an image of the scene can be constructed;

wherein the plurality of X×Y sub-array modules define at least some of the cameras in an M×N arrangement of cameras; and
a processor;
wherein the processor is configured to construct an image of the scene using image data generated by each of the sub-array modules.

6 . The array camera of claim 5 , wherein X is 1 and M is 1.

7 . The array camera of claim 5 , wherein the plurality of X×Y sub-array modules define an M×N arrangement of cameras.

8 . The array camera of claim 5 , further comprising circuitry that aggregates the image data generated by each of the sub-array modules into a single MIPI output, and provides the MIPI output to the processor so that the processor can construct an image of the scene.

9 . The array camera of claim 5 , further comprising a parallax disparity resolution module, wherein the parallax disparity resolution module is configured to receive image data captured by each sub-array module, implement a parallax detection and correction process on the received image data, and output the result for further processing.

10 . The array camera of claim 9 , further comprising circuitry that converts the output of the parallax disparity resolution module into a single MIPI output, and provides the MIPI output to the processor so that the processor can construct an image of the scene.

11 . The array camera of claim 10 , wherein the parallax disparity resolution module comprises a processor and memory, wherein the memory contains software to configure the processor to act as a parallax disparity resolution module.

12 . The array camera of claim 10 , wherein the parallax disparity resolution module is a hardware parallax disparity resolution module.

13 . The array camera of claim 5 , wherein M and N are each greater than or equal to 2.

14 . The array camera of claim 5 , wherein at least two of the plurality of sub-array modules are adjoined to the interconnects of a single substrate, and can thereby output image data through the interconnects.

15 . The array camera of claim 14 , wherein each of the plurality of sub-array modules are adjoined to the interconnects of a single substrate, and can thereby output image data through the interconnects.

16 . The array camera of claim 15 , wherein the substrate is optically transparent.

17 . The array camera of claim 16 , wherein the substrate is glass.

18 . The array camera of claim 15 , wherein the substrate is ceramic with through-holes that clear the optical path.

19 . The array camera of claim 5 , wherein at least one sub-array module is embodied within a single monolithic structure.

20 . The array camera of claim 5 , wherein each sub-array module is embodied within a single respective monolithic structure.

Assignees

• Pelican Imaging Corp

Inventors

• Venkataraman Kartik
• Gallagher Paul
• Lelescu Dan
• Mcmahon Andrew Kenneth John
• Duparre Jacques
• Pain Bedabrata

Classifications

• H04N23/51 Primary

  Housings · CPC title

• H04N25/701

  Line sensors · CPC title

• H04N25/70

  SSIS architectures; Circuits associated therewith · CPC title

• H04N23/13 Primary

  with multiple sensors · CPC title

• H04N23/11

  for generating image signals from visible and infrared light wavelengths · CPC title