Integrated chip and manufacturing method therefor, and full-color integrated chip and display panel
US-12183868-B2 · Dec 31, 2024 · US
US2016268474A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016268474-A1 |
| Application number | US-201514842601-A |
| Country | US |
| Kind code | A1 |
| Filing date | Sep 1, 2015 |
| Priority date | Mar 9, 2015 |
| Publication date | Sep 15, 2016 |
| Grant date | — |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
According to one embodiment, a semiconductor light emitting device includes a base body, first to third semiconductor layers, a first conductive layer, first and second insulating layers. The first semiconductor layer includes a region of a first conductivity type. The second semiconductor layer is provided between the first semiconductor layer and the base body, and has a second conductivity type. The third semiconductor layer is provided between the first and second semiconductor layers. The first conductive layer is provided between a part of the second semiconductor layer and the base body. The first conductive layer is electrically connected to the second semiconductor layer. The first insulating layer is provided between another part of the second semiconductor layer and the base body and between the first conductive layer and the base body. The second insulating layer is provided between the first insulating layer and the base body.
Opening claim text (preview).
What is claimed is: 1 . A semiconductor light emitting device, comprising: a base body; a first semiconductor layer including a region of a first conductivity type; a second semiconductor layer of a second conductivity type, the second semiconductor layer being provided between the first semiconductor layer and the base body; a third semiconductor layer provided between the first semiconductor layer and the second semiconductor layer; a first conductive layer provided between a part of the second semiconductor layer and the base body, the first conductive layer being electrically connected to the second semiconductor layer; a first insulating layer provided between another part of the second semiconductor layer and the base body and between the first conductive layer and the base body; and a second insulating layer provided between the first insulating layer and the base body, a first thickness of the first insulating layer at a first position being smaller than a second thickness of the first insulating layer at a second position, the first insulating layer overlapping the first conductive layer at the first position in a first direction from the second semiconductor layer toward the first semiconductor layer, the first insulating layer not overlapping the first conductive layer at the second position in the first direction, and a second absolute value of a difference between a third thickness of the second insulating layer at the first position and a fourth thickness of the second insulating layer at the second position being smaller than a first absolute value of a difference between the first thickness and the second thickness. 2 . The device according to claim 1 , wherein the second absolute value is smaller than a thickness of the first conductive layer. 3 . The device according to claim 1 , wherein the second absolute value is not more than ½ a thickness of the first conductive layer. 4 . The device according to claim 1 , wherein an absolute value of a difference between the first absolute value and the second absolute value is not less than ½ times and not more than 1.2 times a thickness of the first conductive layer. 5 . The device according to claim 1 , wherein the device further includes a first pad, and a second pad, and the first semiconductor layer is disposed between the first pad and the third semiconductor layer, and the first pad is electrically connected to the first semiconductor layer, a part of the first conductive layer is disposed between the part of the second semiconductor layer and the base body, another part of the first conductive layer is disposed between the second pad and the base body, and the second pad is electrically connected to the another part of the conductive layer. 6 . The device according to claim 5 , wherein a distance between the first pad and the first conductive layer is not less than 1.5 μm and not more than 30 μm. 7 . The device according to claim 5 , wherein at least a part of the second pad overlaps at least a part of a stacked body including the first semiconductor layer, the third semiconductor layer, and the second semiconductor layer in a direction intersecting the first direction. 8 . The device according to claim 5 , wherein the first conductive layer includes a first metal layer and a second metal layer, the first metal layer is provided between a part of the second metal layer and the second semiconductor layer, a fifth thickness of the first insulating layer at a third position is smaller than a sixth thickness of the first insulating layer at a fourth position, the first insulating layer overlaps the first metal layer at the third position in the first direction, the first insulating layer overlaps the first conductive layer but does not overlap the first metal layer at the fourth position in the first direction, and a fourth absolute value of a difference between a seventh thickness of the second insulating layer at the third position and an eighth thickness of the second insulating layer at the fourth position is smaller than a third absolute value of a difference between the fifth thickness and the sixth thickness. 9 . The device according to claim 8 , wherein the fourth absolute value is smaller than a thickness of the first metal layer. 10 . The device according to claim 5 , wherein the first conductive layer includes a first metal layer and a second metal layer, a part of the first metal layer is provided between the second metal layer and the second semiconductor layer, a fifth thickness of the first insulating layer at a third position is smaller than a sixth thickness of the first insulating layer at a fourth position, the first insulating layer overlaps the part of the first metal layer at the third position in the first direction, the first insulating layer overlaps the first metal layer but does not overlap the second metal layer at the fourth position in the first direction, and a fourth absolute value of a difference between a seventh thickness of the second insulating layer at the third position and an eighth thickness of the second insulating layer at the fourth position is smaller than a third absolute value of a difference between the fifth thickness and the sixth thickness. 11 . The device according to claim 10 , wherein the fourth absolute value is smaller than a thickness of the second metal layer. 12 . The device according to claim 8 , wherein an absolute value of a difference between the third absolute value and the fourth absolute value is not less than ½ times and not more than 1.2 times a thickness of the first metal layer. 13 . The device according to claim 8 , wherein the part of the first conductive layer includes the first metal layer and the part of the second metal layer, and the another part of the first conductive layer includes another part of the second metal layer. 14 . A semiconductor light emitting device, comprising: a base body; a first semiconductor layer spaced apart from the base body in a first direction, the first semiconductor layer including a first semiconductor region and a second semiconductor region juxtaposed with the first semiconductor region in a direction intersecting the first direction, and also including a region of a first conductivity type; a second semiconductor layer of a second conductivity type, the second semiconductor layer being provided between the second semiconductor region and the base body; a third semiconductor layer provided between the first semiconductor layer and the second semiconductor layer; a first insulating layer provided between the first semiconductor region and the base body and between the second semiconductor layer and the base body; and a second insulating layer provided between the first insulating layer and the base body, a first thickness of the first insulating layer at a first position being smaller than a second thickness of the first insulating layer at a second position, the first insulating layer overlapping the second semiconductor region at the first position in the first direction, the first insulating layer overlapping the first semiconductor region at the second position in the first direction, and a second absolute value of a difference between a third thickness of the second insulating layer at the first position and a fourth thickness of the second insulating layer at the second position being smaller than a first absolute value of a difference between the first thickness and the second thickness. 15 . The device according to claim 14 , wherein the device further includes a fi
Bonding of wafers · CPC title
Coatings, e.g. passivation layers or antireflective coatings · CPC title
Bodies · CPC title
characterised by their shape · CPC title
Electricity · mapped topic
Related publications grouped by family.
Answers are generated from the same data shown on this page.