Semiconductor device having fin-type field effect transistor and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016268394-A1
Application number	US-201615165931-A
Country	US
Kind code	A1
Filing date	May 26, 2016
Priority date	Apr 25, 2014
Publication date	Sep 15, 2016
Grant date	—

Abstract

A semiconductor device includes a substrate having a first region and a second region, a first MOS transistor including a first fin structure and a first gate electrode in the first region, the first fin structure having a first buffer pattern, a second buffer pattern, and a first channel pattern which are sequentially stacked on the substrate, and a second MOS transistor including a second fin structure and a second gate electrode in the second region, the second fin structure having a third buffer pattern and a second channel pattern which are sequentially stacked on the substrate. Related fabrication methods are also discussed.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, the method comprising:
providing a substrate having a first region and a second region; forming a plurality of first fin structures on the substrate, the plurality of first fin structures including a first buffer pattern and a first channel pattern; forming a device isolation pattern filling a plurality of gaps between the plurality of first fin structures; forming a plurality of trenches in the device isolation pattern formed in the second region by removing upper portions of the first fin structures, the plurality of trenches exposing the first buffer pattern formed in the second region; and forming a plurality of second fin structures on the first buffer pattern formed in the second region, the plurality of second fin structures including a second buffer pattern and a second channel pattern, wherein the first and second buffer patterns and the first and second channel patterns comprise a semiconductor material including germanium (Ge).

2 . The method of claim 1 , wherein an upper surface of the first buffer pattern formed in the second region has a lower level than an upper surface of the first buffer pattern formed in the first region.

3 . The method of claim 1 , wherein the plurality of first fin structures further comprises a third buffer pattern between the first buffer pattern and the first channel pattern, the third buffer pattern comprising semiconductor material including germanium (Ge), and
wherein a germanium (Ge) concentration of the third buffer pattern progressively increases from a bottom portion of the third buffer pattern to an upper portion of the third buffer pattern.

4 . The method of claim 3 , wherein a difference of the germanium (Ge) concentrations between the first channel pattern and an upper portion of the third buffer pattern is less than a difference of the germanium (Ge) concentrations between the second channel pattern and an upper portion of the second buffer pattern.

5 . The method of claim 1 , wherein a germanium (Ge) concentration of the second buffer pattern progressively increases from a bottom portion of the second buffer pattern to an upper portion of the second buffer pattern.

6 . The method of claim 5 , wherein a difference of the germanium (Ge) concentrations between the second channel pattern and an upper portion of the second buffer pattern is less than a difference of the germanium (Ge) concentrations between the first channel pattern and an upper portion of the first buffer pattern.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hur Sung Gi
• Kwon Taeyong
• Kim Sangsu
• Choi Jungdal

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title