Semiconductor device and method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-2016268368-A1
Application number	US-201514826656-A
Country	US
Kind code	A1
Filing date	Aug 14, 2015
Priority date	Mar 13, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a gate electrode, and a gate insulating layer. The first semiconductor region includes first portions and second portions. A length in a second direction of the second portion is longer than a length in the second direction of the first portion. The plurality of first portions and the plurality of second portions are provided alternately in a third direction. Part of the third semiconductor region is located between the second portions. An impurity concentration of the second conductivity type of the third semiconductor region is lower than an impurity concentration of the second conductivity type of the second semiconductor region.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first semiconductor region of a first conductivity type including a plurality of first portions and a plurality of second portions, each of the first portions extending in a first direction, each of the second portions extending in the first direction, a length in a second direction of the second portion being longer than a length in the second direction of the first portion, the second direction being orthogonal to the first direction, and the plurality of first portions and the plurality of second portions being provided alternately in a third direction orthogonal to the first direction and the second direction; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the second conductivity type provided on the second semiconductor region, part of the third semiconductor region being located between the second portions, and impurity concentration of the second conductivity type of the third semiconductor region being lower than impurity concentration of the second conductivity type of the second semiconductor region; a fourth semiconductor region of the first conductivity type selectively provided on the third semiconductor region; a gate electrode provided on the second portion; and a gate insulating layer provided between the gate electrode and each of the second portion, the second semiconductor region, the third semiconductor region, and the fourth semiconductor region.

2 . The device according to claim 1 , wherein part of the second semiconductor region and part of the third semiconductor region are provided between the first portion and the fourth semiconductor region in the first direction.

3 . The device according to claim 1 , wherein
the third semiconductor region includes a fifth portion and a sixth portion, the fifth portion is provided between the second portions, the sixth portion is provided between the first portion and the fifth portion, a length in the second direction of the fifth portion is longer than thickness of the second semiconductor region, and a length in the second direction of the sixth portion is shorter than the thickness of the second semiconductor region.

4 . The device according to claim 1 , further comprising:
a void surrounded with the third semiconductor region, wherein at least part of the void is located between the second portions in the third direction.

5 . A method for manufacturing a semiconductor device, comprising:
forming a first opening in a first semiconductor layer of a first conductivity type; forming a second semiconductor layer of a second conductivity type along a surface of the first semiconductor layer; forming a third semiconductor layer filling the first opening on the second semiconductor layer, impurity concentration of the second conductivity type of the third semiconductor layer being lower than impurity concentration of the second conductivity type of the second semiconductor layer; forming a second opening penetrating through the second semiconductor layer and the third semiconductor layer to a region of the first semiconductor layer other than a region in which the first opening is formed; forming an insulating layer along an inner wall of the second opening; forming a conductive layer on the insulating layer; and forming a first semiconductor region of the first conductivity type in part of a surface of the third semiconductor layer.

6 . The method according to claim 5 , wherein
in the forming the first opening, the first opening is formed in a plurality, the plurality of first openings are arranged in a first direction, and each of the first openings extends in a second direction orthogonal to the first direction, the third semiconductor layer fills the plurality of first openings, in the forming the second opening, the second opening is formed in a plurality, the plurality of second openings are arranged in the first direction, and each of the second openings extends in the second direction, and the insulating layer lies along an inner wall of the plurality of second openings.

7 . The method according to claim 6 , wherein in the forming the conductive layer, the conductive layer fills the plurality of second openings.

8 . The method according to claim 7 , further comprising:
removing part of the conductive layer to divide the conductive layer into a plurality and to provide the respective conductive layers inside the respective second openings.

9 . The method according to claim 8 , wherein in the forming the first semiconductor region, the first semiconductor region is formed in a plurality, and at least part of each of the first semiconductor regions is located between the conductive layers.

10 . The method according to claim 5 , wherein in the forming the first semiconductor region, the first semiconductor region is formed so that part of the second semiconductor layer of the second conductivity type remains between the first semiconductor region and the first semiconductor layer.

11 . The method according to claim 5 , wherein the third semiconductor layer includes a void.

Assignees

• Toshiba Kk

Inventors

• Matsuda Shizue
• Yokoyama Noboru

Classifications

• H10D62/051

  Forming charge compensation regions, e.g. superjunctions · CPC title

• H10D62/111 Primary

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D30/668

  having trench gate electrodes, e.g. UMOS transistors · CPC title